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    • 1. 发明申请
    • Power distribution and biasing in RF switch-mode power amplifiers
    • RF开关模式功率放大器的功率分配和偏置
    • US20070046377A1
    • 2007-03-01
    • US11233397
    • 2005-09-21
    • Ronald Meck
    • Ronald Meck
    • H03F3/04
    • H03F1/0261H03F1/30H03F3/195H03F2200/408
    • Methods of and apparatus for distributing power and biasing RF PAs. A power distribution network includes a pre-final amplifier stage power distribution network and a final amplifier stage power distribution network. The pre-final amplifier stage power distribution network includes one or more pre-final amplifier stage power distribution branches, which may be configured to distribute power from one or more pre-final amplifier power supplies to one or more pre-final amplifier stages. Each pre-final amplifier stage power distribution branch comprises a π C-R-C network coupled to an inductive load. A final amplifier stage power distribution network is configured to distribute power from a final amplifier stage power supply to a final stage of the amplifier circuit.
    • 用于分配功率和偏置RF PA的方法和设备。 配电网络包括一个最终的放大器级配电网络和一个最终的放大器级配电网络。 预最终放大器级配电网络包括一个或多个预最终放大器级功率分配分支,其可被配置为将功率从一个或多个预最终放大器电源分配到一个或多个预最终放大器级。 每个预最终的放大器级配电支路包括耦合到电感负载的pi C-R-C网络。 最后的放大器级配电网络被配置为将功率从最终放大器级电源分配到放大器电路的最后级。
    • 2. 发明申请
    • Apparatus and method for dynamically clocking a loop filter in a digital communications device
    • 用于在数字通信设备中动态计时环路滤波器的装置和方法
    • US20070104289A1
    • 2007-05-10
    • US11268798
    • 2005-11-08
    • Paul LiangRajesh Patel
    • Paul LiangRajesh Patel
    • H04L27/00
    • H04L27/12H04L27/20
    • A transmitter has a signal generator, an amplifier, a detection circuit, a comparison circuit, a loop filter, and an adjustable clock. The signal generator produces a signal. The signal is produced with a first frequency characteristic and contains frequency-related information. The detection circuit detects the first frequency-related characteristic and generates an associated signal in response. A comparison circuit compares the signal from the detection circuit and another signal. It outputs a signal associated with the difference between the two. A loop filter receives the output of the comparison circuit and generates a signal to the signal generator in. The loop filter is clocked at a second frequency by a signal from a clock circuit. The clock circuit can compare the first frequency and the second frequency, and can change the second frequency based upon a relationship between the two frequencies.
    • 发射机具有信号发生器,放大器,检测电路,比较电路,环路滤波器和可调节时钟。 信号发生器产生信号。 该信号产生具有第一频率特性并且包含频率相关信息。 检测电路检测第一频率相关特性并产生响应的相关信号。 比较电路将来自检测电路的信号与另一信号进行比较。 它输出与两者之间的差异相关联的信号。 环路滤波器接收比较电路的输出并产生信号到信号发生器。环路滤波器以来自时钟电路的信号以第二频率被计时。 时钟电路可以比较第一频率和第二频率,并且可以基于两个频率之间的关系来改变第二频率。
    • 3. 发明申请
    • Apparatus and method for multi-phase digital sampling
    • 多相数字采样装置及方法
    • US20070071142A1
    • 2007-03-29
    • US11282322
    • 2005-11-18
    • Wendell Sander
    • Wendell Sander
    • H04L27/06
    • G01R23/005H03D13/00
    • A method and apparatus for determining a relationship between an input signal frequency and a reference signal frequency is envisioned. The system derives a plurality of internal reference signals from the reference signal. The internal reference signals are provided to a level detection circuit which in turn samples the input signal a number of times within a period of time. Values associated with these samples are stored, as is one value of a sample from a previous period. The stored samples are correlated, and a relationship between the input signal frequency and the reference signal frequency is derived.
    • 可以想到用于确定输入信号频率和参考信号频率之间的关系的方法和装置。 该系统从参考信号中导出多个内部参考信号。 内部参考信号被提供给电平检测电路,电平检测电路又在一段时间内对输入信号多次进行采样。 存储与这些样品相关联的值,以及来自前一个周期的样品的一个值。 存储的样本相关,并且导出输入信号频率和参考信号频率之间的关系。
    • 4. 发明申请
    • High-efficiency modulating RF amplifier
    • US20060293002A1
    • 2006-12-28
    • US11514150
    • 2006-09-01
    • Earl McCune
    • Earl McCune
    • H04B1/04H01Q11/12
    • H03C1/36H01Q1/243H03F1/02H03F1/0205H03F1/0211H03F1/0227H03F1/0244H03F1/0277H03F1/32H03F3/2178H03F3/24H03F2200/504H03G3/004H03G3/3047H04B2001/0408H04B2001/045
    • The present invention, generally speaking, provides for high-efficiency power control of a high-efficiency (e.g., hard-limiting or switch-mode) power amplifier in such a manner as to achieve a desired modulation. In one embodiment, the spread between a maximum frequency of the desired modulation and the operating frequency of a switch-mode DC-DC converter is reduced by following the switch-mode converter with an active linear regulator. The linear regulator is designed so as to control the operating voltage of the power amplifier with sufficient bandwidth to faithfully reproduce the desired amplitude modulation wave-form. The linear regulator is further designed to reject variations on its input voltage even while the output voltage is changed in response to an applied control signal. This rejection will occur even though the variations on the input voltage are of commensurate or even lower frequency than that of the controlled output variation. Amplitude modulation may be achieved by directly or effectively varying the operating voltage on the power amplifier while simultaneously achieving high efficiency in the conversion of primary DC power to the amplitude modulated output signal. High efficiency is enhanced by allowing the switch-mode DC-to-DC converter to also vary its output voltage such that the voltage drop across the linear regulator is kept at a low and relatively constant level. Time-division multiple access (TDMA) bursting capability may be combined with efficient amplitude modulation, with control of these functions being combined. In addition, the variation of average output power level in accordance with commands from a communications system may also be combined within the same structure.
    • 5. 发明申请
    • Data sampler for digital frequency/phase determination
    • 用于数字频率/相位确定的数据采样器
    • US20060182213A1
    • 2006-08-17
    • US11400449
    • 2006-04-06
    • Brian Sander
    • Brian Sander
    • H04L7/00
    • H04L7/0334
    • The present invention, generally speaking, provides a digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may e derived from a communications signal, for example. The rate of the unknown clock signal may exceed the rate of the known clock signal. In an exemplary embodiment, an “alias” value (e.g., an integer 1, 2, 3, etc.) is applied to the circuit as an indication of the expected frequency range of the unknown clock signal. The number stream is formed accordingly.
    • 一般而言,本发明提供一种数字电路和方法,用于形成用于数字或数字化信号的频率和/或相位比较的数字流,这里称为时钟信号,其中通常一个时钟信号是已知的时钟信号, 另一个时钟信号是未知的时钟信号。 例如,可以从通信信号导出未知时钟信号。 未知时钟信号的速率可能会超过已知时钟信号的速率。 在示例性实施例中,将“别名”值(例如,整数1,2,3等)作为未知时钟信号的预期频率范围的指示被施加到电路。 相应地形成数字流。
    • 6. 发明申请
    • Digital time alignment in a polar modulator
    • 极坐标调制器中的数字时间校准
    • US20040247041A1
    • 2004-12-09
    • US10454906
    • 2003-06-04
    • Tropian, Inc., a California Corporation
    • Thomas E. BiedkaWayne S. LeeGary L. Do
    • H04L027/04H04L027/12H04L027/20H03C003/00H03K007/06
    • H04L27/361H03C5/00
    • Methods of and apparatus for digitally controlling, with sub-sample resolution, the relative timing of the magnitude and phase paths in a polar modulator. The timing resolution is limited by the dynamic range of the system as opposed to the sample rate. The methods and apparatus of the invention use a digital filter to approximate a sub-sample time delay. Various techniques for approximating a sub-sample time delay using digital signal processing may be used to achieve the approximation. Ideally, the filter will have an all-pass magnitude response and a linear phase response. In practice, the magnitude may be low-pass and the phase may not be perfectly linear. Such deviation from the ideal response will introduce some distortion. However, this distortion may be acceptably small depending on the particular signal being processed.
    • 利用子样本分辨率数字控制的方法和装置,极坐标调制器中的幅度和相位路径的相对定时。 定时分辨率受系统动态范围的限制,而不是采样率。 本发明的方法和装置使用数字滤波器近似子采样时间延迟。 可以使用用于使用数字信号处理近似子采样时间延迟的各种技术来实现近似。 理想情况下,滤波器将具有全通幅度响应和线性相位响应。 实际上,幅度可能是低通,相位可能不是完全线性的。 这种偏离理想的反应会引入一些失真。 然而,根据正在处理的特定信号,该失真可能是可接受的。
    • 7. 发明申请
    • High-efficiency modulating RF amplifier
    • US20060293003A1
    • 2006-12-28
    • US11514198
    • 2006-09-01
    • Earl McCune
    • Earl McCune
    • H04B1/04H01Q11/12
    • H03C1/36H01Q1/243H03F1/02H03F1/0205H03F1/0211H03F1/0227H03F1/0244H03F1/0277H03F1/32H03F3/2178H03F3/24H03F2200/504H03G3/004H03G3/3047H04B2001/0408H04B2001/045
    • The present invention, generally speaking, provides for high-efficiency power control of a high-efficiency (e.g., hard-limiting or switch-mode) power amplifier in such a manner as to achieve a desired modulation. In one embodiment, the spread between a maximum frequency of the desired modulation and the operating frequency of a switch-mode DC-DC converter is reduced by following the switch-mode converter with an active linear regulator. The linear regulator is designed so as to control the operating voltage of the power amplifier with sufficient bandwidth to faithfully reproduce the desired amplitude modulation wave-form. The linear regulator is further designed to reject variations on its input voltage even while the output voltage is changed in response to an applied control signal. This rejection will occur even though the variations on the input voltage are of commensurate or even lower frequency than that of the controlled output variation. Amplitude modulation may be achieved by directly or effectively varying the operating voltage on the power amplifier while simultaneously achieving high efficiency in the conversion of primary DC power to the amplitude modulated output signal. High efficiency is enhanced by allowing the switch-mode DC-to-DC converter to also vary its output voltage such that the voltage drop across the linear regulator is kept at a low and relatively constant level. Time-division multiple access (TDMA) bursting capability may be combined with efficient amplitude modulation, with control of these functions being combined. In addition, the variation of average output power level in accordance with commands from a communications system may also be combined within the same structure.
    • 8. 发明申请
    • Apparatus and method for operating a variable segment oscillator
    • 用于操作可变段振荡器的装置和方法
    • US20070159261A1
    • 2007-07-12
    • US11326645
    • 2006-01-06
    • Wayne Lee
    • Wayne Lee
    • H03L7/00
    • H03L7/099H03L7/10H03L7/113
    • This disclosure is directed to a communications device having a comparator that receives a signal associated with an output and produces a signal associated with a difference between a reference signal and the output signal. A loop filter is coupled to the comparator and accepts the difference signal. An oscillator is coupled to the loop filter and accepts the loop filter signal. It produces a signal with a frequency-characteristic in response. The oscillator can operate at a plurality of segments. A segment selection circuit is coupled to the oscillator. It determines which segment will be selected based upon a signal associated with an expected frequency characteristic, and outputs a signal associated with the particular segment. In response, the oscillator can then change its operational state to the particular segment. An amplification circuit is coupled to the oscillator, and produces an output signal with the particular frequency characteristic.
    • 本公开针对具有比较器的通信设备,该比较器接收与输出相关联的信号,并产生与参考信号和输出信号之间的差相关的信号。 环路滤波器耦合到比较器并接收差分信号。 振荡器耦合到环路滤波器并接受环路滤波器信号。 它产生响应频率特性的信号。 振荡器可以在多个段工作。 段选择电路耦合到振荡器。 它基于与预期频率特性相关联的信号来确定哪个段将被选择,并且输出与特定段相关联的信号。 作为响应,振荡器然后可以将其操作状态改变为特定段。 放大电路耦合到振荡器,并产生具有特定频率特性的输出信号。