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1. 发明专利

MY6900237A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION 未知
公开(公告)号：MY6900237A
公开(公告)日：1969-12-31
申请号：MY6900237
申请日：1969-12-31
申请人： TEXAS INSTRUMENT INCORPORATED
IPC分类号： H01L23/24 , H01L23/495 , H01L1/00
摘要： 1,014,735. Semi-conductor devices. TEXAS INSTRUMENTS Inc. Oct. 19, 1962 [Oct. 20, 1961], No. 30175/65. Divided out of 1,014,734. Heading H1K. An encapsulated PN junction semi-conductor device, such as described in Specification 1,014,734, comprises a substrate having a substantially flat surface and a semi-conductor wafer on the flat surface. The wafer has a plurality of PN junctions all of which are in the vicinity of one major wafer face and are spaced from the opposite major wafer face. An enclosure including the substrate surrounds the wafer and electrical connections exterior of the enclosure extend into the interior to connect ohmically to various semi-conductor zones of the wafer. The connections include a plurality of spaced coplanar flat conductors on the substantially flat surface and a respective plurality of spaced coplanar elongate flat conductors. The entire opposite major wafer face ohmically rests on one of the spaced coplanar flat conductors and wires ohmically connect between the semi-conductor zone of the one major wafer face and the other ones of the spaced coplanar flat conductors.

2. 发明专利

MY6900290A MINIATURE SEMICONDUCTOR DEVICES 未知
公开(公告)号：MY6900290A
公开(公告)日：1969-12-31
申请号：MY6900290
申请日：1969-12-31
申请人： TEXAS INSTRUMENT INCORPORATED
IPC分类号： H01L21/00 , H01L21/033 , H01L21/18 , H01L21/3063 , H01L21/316 , H01L21/76 , H01L21/761 , H01L21/82 , H01L21/8222 , H01L23/29 , H01L23/522 , H01L27/06 , H01L27/07 , H01L27/08 , H01L29/00 , H01L29/8605 , H01L29/92 , H01L29/93 , H01L29/94 , H03K3/281 , H03K3/286 , H01L23/52 , H01L29/86
摘要： 945,749. Semi-conductor devices. TEXAS INSTRUMENTS Inc. Feb. 2, 1960 [Feb. 6, 1959], No. 32744/63. Divided out of 945,734. Heading H1K. The subject matter of this Specification is included in Specification 945,734 from which the present Specification is divided but the claims relate to a device comprising a semi-conductor body with three superposed regions of alternate conductivity types forming a pair of PN junctions extending to a surface of the body and there defining two enclosed areas one within the other, with an insulating oxide of a semi-conductor covering selected parts of said surface, first and second ohmic contacts secured to said surface on opposite sides of the inner PN junction and a third ohmic contact secured to the third region. Specifications 945,737, 945,738, 945,739, 945,740, 945,741, 945,742, 945,743, 945,744, 945,745, 945,746, 945,747 and 945,748 also are referred to.

3. 发明专利

MY6900277A MARINE SEISMIC EXPLORATION SYSTEM 未知
公开(公告)号：MY6900277A
公开(公告)日：1969-12-31
申请号：MY6900277
申请日：1969-12-31
申请人： TEXAS INSTRUMENT INCORPORATED
IPC分类号： G01V1/36 , G01V1/38

4. 发明专利

MY6900231A METHOD FOR MAKING GRADED COMPOSITION MEXED COMPOUND SEMICONDUCTOR MATERIALS 未知
公开(公告)号：MY6900231A
公开(公告)日：1969-12-31
申请号：MY6900231
申请日：1969-12-31
申请人： TEXAS INSTRUMENT INCORPORATED
IPC分类号： B01J19/00 , C01G30/00 , C23C16/00 , C30B25/02 , H01L21/00 , H01L29/207 , C01B25/08

5. 发明申请

WO2017151827A1 OUTPUT DRIVE WITH POWER DOWN PROTECTION 审中-公开
标题翻译：输出驱动器具有掉电保护功能
公开(公告)号：WO2017151827A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/020294
申请日：2017-03-01
申请人： TEXAS INSTRUMENT INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： WU, Xiaoju , KELOTH, Rajesh , PRASAD, Sudheer
IPC分类号： H01L29/94 , H01L29/772 , H01L21/8224 , H02H7/09
摘要： In described examples, an interface device (300) includes an NPN structure (Ql) along a horizontal surface of a p-doped substrate (204). The NPN structure (300) has a first n-doped region (242) coupled to an output terminal (106), a p-doped region (232, 243, 245) surrounding the first n-doped region (242) and coupled to the output terminal (107), and a second n-doped region (244) separated from the first n-doped region (242) by the p-doped region (243). The interface device (300) also includes a PNP structure (230) along a vertical depth of the p-doped substrate (204). The PNP structure (230) includes the p-doped region (243), an n-doped layer (234) under the p-doped region (243), and the p-doped substrate (204). Advantageously, the interface device (300) can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.
摘要翻译：在所描述的示例中，界面装置（300）包括沿着p掺杂衬底（204）的水平表面的NPN结构（Q1）。 NPN结构（300）具有耦合到输出端（106）的第一n掺杂区（242），围绕第一n掺杂区（242）的p掺杂区（232,243,245），并耦合到输出端（107）以及通过p掺杂区（243）与第一n掺杂区（242）隔开的第二n掺杂区（244）。界面装置（300）还包括沿着p掺杂衬底（204）的垂直深度的PNP结构（230）。 PNP结构（230）包括p掺杂区域（243），p掺杂区域（243）下方的n掺杂层（234）以及p掺杂衬底（204）。有利的是，接口设备（300）可以承受高电压摆动（正向和负向），防止下沉并获得大的负载电流，并且避免在断电操作期间进入低电阻模式。

6. 发明申请

WO2014179809A1 GALLIUM NITRIDE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：氮化镓场效应晶体管
公开(公告)号：WO2014179809A1
公开(公告)日：2014-11-06
申请号：PCT/US2014/036842
申请日：2014-05-05
申请人： TEXAS INSTRUMENT INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： HAIDER, Asad, Mahmood , JOH, Jungwoo
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/7787 , H01L21/28264 , H01L21/28575 , H01L29/2003 , H01L29/42368 , H01L29/452 , H01L29/4975 , H01L29/518 , H01L29/66462
摘要： A semiconductor device (100) may be formed by forming a silicon-containing gate dielectric layer (108) over a semiconductor layer (104). A gate metal layer is formed over the gate dielectric layer (108); the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate (112). Source and drain contact holes (116) are subsequently formed, and contact metal (118) is formed and patterned in the contact holes (116). A subsequent contact anneal heats the contact metal (118) and gate (112) for at least 30 seconds at a temperature of at least 750 °C.
摘要翻译：半导体器件（100）可以通过在半导体层（104）上形成含硅栅极电介质层（108）而形成。在栅介电层（108）上方形成栅极金属层; 栅极金属层在形成期间包括2原子％至10原子％的硅。图案化栅极金属层以形成金属栅极（112）。随后形成源极和漏极接触孔（116），并且在接触孔（116）中形成并图案化接触金属（118）。随后的接触退火在至少750℃的温度下将接触金属（118）和浇口（112）加热至少30秒。

7. 发明申请

WO2008115937A1 DOPED WGE TO FORM DUAL METAL GATES 审中-公开
公开(公告)号：WO2008115937A1
公开(公告)日：2008-09-25
申请号：PCT/US2008/057392
申请日：2008-03-19
申请人： TEXAS INSTRUMENT INCORPORATED , VISOKAY, Mark, R. , RAMIN, Manfred , PAS, Michael, Francis
发明人： VISOKAY, Mark, R. , RAMIN, Manfred , PAS, Michael, Francis
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/28026 , H01L21/28088 , H01L27/092 , H01L29/4966
摘要： A method (200) of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer (204) above a semiconductor body, forming a work function adjusting layer (206) on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer (208) above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing (210) the semiconductor device, depositing a metal nitride barrier layer (212) on the tungsten germanium layer, depositing a polysilicon layer (214) over the metal nitride, patterning the poly silicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain (222) on opposite sides of the gate structure.
摘要翻译：一种在半导体器件中制造双金属栅极结构的方法（200），所述方法包括在半导体主体上方形成栅极电介质层（204），在PMOS的电介质栅极层上形成功函数调节层（206）在所述PMOS区域中的所述功函数调节材料的上方沉积钨锗栅电极层，在所述半导体器件的所述NMOS区域退火（210）中沉积所述栅极电介质上方的钨锗栅电极层，沉积金属氮化物在所述钨锗层上形成阻挡层（212），在所述金属氮化物上沉积多晶硅层（214），对所述多晶硅层，所述金属氮化物层，所述钨锗层，功函数调整层和所述栅介电层进行构图栅极结构，并且在栅极结构的相对侧上形成源极/漏极（222）。

8. 发明申请

WO2017151648A1 BIO-SENSING DEVICE WITH AMBIENT LIGHT CANCELLATION 审中-公开
标题翻译：具有环境光取消功能的生物感应装置
公开(公告)号：WO2017151648A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/019994
申请日：2017-02-28
申请人： TEXAS INSTRUMENT INCORPORATED , TEXAS INSTRUMENT JAPAN LIMITED
发明人： AHMED, Hussam , VENKATARAMAN, Jagannathan , OSWAL, Sandeep, Kesrimal , AROUL, Antoine, Lourdes Praveen , TIPPANA, Hari, Babu , UDUPA, Anand, Hariraj
IPC分类号： G01D18/00 , A61B5/024
摘要： In described examples, a bio-sensing device (100) calibrates a time period used to make bio-physical measurements. The device (100) initiates a light source sense phase followed by a first ambient sense phase and a second ambient sense phase. In the light source sense phase, the device (100) is configured to receive a digital value indicative of current through a photodetector (122) while a light source circuit (120) is enabled. In each of the first and second ambient sense phases, the device (100) is configured to receive digital values while the light source circuit (120) is disabled. The device (100) iteratively varies the time period between the phases until the digital value received during the first ambient sense phase is within a threshold of the digital value received during the second ambient sense phase. It then applies the same time separation between the light source sense phase and the ambient phase to equalize the magnitude of the ambient light in the two phases.
摘要翻译：在所描述的示例中，生物感测设备（100）校准用于进行生物物理测量的时间段。设备（100）启动光源感测阶段，之后是第一环境感测阶段和第二环境感测阶段。在光源感测阶段中，设备（100）被配置为在光源电路（120）被启用时接收指示通过光电检测器（122）的电流的数字值。在第一和第二环境感测阶段中的每一个中，设备（100）被配置为在光源电路（120）被禁用时接收数字值。设备（100）迭代地改变相位之间的时间段，直到在第一环境感测阶段期间接收的数字值在第二环境感测阶段期间接收的数字值的阈值内。然后在光源感应阶段和环境阶段之间应用相同的时间间隔来均衡两个阶段中的环境光的大小。

9. 发明申请

WO2013116751A1 DYNAMIC POWER MANAGEMENT IN REAL-TIME SYSTEMS 审中-公开
标题翻译：实时系统动态电源管理
公开(公告)号：WO2013116751A1
公开(公告)日：2013-08-08
申请号：PCT/US2013/024474
申请日：2013-02-01
申请人： TEXAS INSTRUMENT INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： LEE, Sejoong , CHOI, Soon-hyeok , LU, Xiaolin
IPC分类号： G06F1/32
CPC分类号： G06F1/32 , G06F1/3206 , G06F1/3243 , G06F9/48 , G06F11/34 , Y02D10/152 , Y02D50/20
摘要： A Dynamic Sleep Controller (220) reduces power consumption by a processor (CPU 202) in a computer system by determining a maximum number of times (token count) that the processor (CPU 202) can incur a start-up delay after being placed into a low- power mode during a token period of time when executing a task for a token period of time. The processor (CPU 202) may be placed into the low-power mode by a sleep request signal (222) sent to a power and clock controller (230) while the processor (CPU 202) is executing the task in response to an idle indicator only if a current value of the token count assigned to the task is greater than zero. The current value of the token count is decremented each time the processor incurs a start-up delay in response to being awakened from the low-power mode. The current token count is reset to match the assigned token count at the end of each token period. Furthermore, wakeup may be anticipated to allow the processor (CPU 202) to be awakened preemptively by a preemptive wakeup signal (224) sent to an interrupt controller (210) which sends a wakeup request (214) to a power and clock controller (230).
摘要翻译：动态睡眠控制器（220）通过确定处理器（CPU 202）在被放入之后可能引起启动延迟的最大次数（令牌计数）来减少计算机系统中的处理器（CPU 202）的功耗。在执行令牌时间段的任务期间的令牌时段期间的低功率模式。处理器（CPU 202）可以通过发送到电力和时钟控制器（230）的睡眠请求信号（222）而置于低功率模式，同时处理器（CPU 202）响应于空闲指示符执行任务只有分配给任务的令牌计数的当前值大于零。每当处理器响应于从低功率模式唤醒而引起启动延迟时，令牌计数的当前值递减。当前令牌计数被重置为与每个令牌周期结束时分配的令牌计数相匹配。此外，可以预期唤醒允许处理器（CPU 202）通过发送到向中断控制器（210）发送唤醒请求（214）的抢占唤醒信号（224）来抢先唤醒，以向电源和时钟控制器（230）发送唤醒请求）。

10. 发明申请

WO2008147803A1 PROBE TEST SYSTEM AND METHOD FOR TESTING A SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：用于测试半导体封装的探测测试系统和方法
公开(公告)号：WO2008147803A1
公开(公告)日：2008-12-04
申请号：PCT/US2008/064342
申请日：2008-05-21
申请人： TEXAS INSTRUMENT INCORPORATED , MATSUNAMI, Akira
发明人： MATSUNAMI, Akira
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： G01R31/2889
摘要： In a method and system (100) for testing a device under test (DUT) (190), a replaceable test connector (RTC) (120) is disposed between a probe pin (114) of a tester (110) and the DUT. The RTC includes an upper test bond pad that is electrically coupled to a lower test bond pad. The probe pin is capable of being positioned to make a physical contact with the upper test bond pad, the physical contact enabling an electrical coupling there between. The lower test bond pad is capable of being positioned to make physical contact with a device bond pad of the DUT, the physical contact enabling an electrical coupling between the lower test bond pad and the device bond pad. The device bond pad is protected from potential damage from the probe pin by the RTC that is replaceable.
摘要翻译：在用于测试被测设备（DUT）（190）的方法和系统（100）中，可替换的测试连接器（RTC）（120）设置在测试器（110）的探针（114）和DUT之间。 RTC包括电耦合到下测试接合焊盘的上测试接合焊盘。探针能够被定位成与上测试接合焊盘进行物理接触，物理接触能够在其间进行电耦合。下测试接合焊盘能够定位成与DUT的器件接合焊盘物理接触，物理接触使得能够在下测试接合焊盘和器件接合焊盘之间进行电耦合。保护器件接合焊盘免受可更换的RTC的探头引脚的潜在损坏。

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