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1. 发明授权

US07733990B2 Receiver with improved sample granularity 有权
标题翻译：接收器具有改进的样品粒度
公开(公告)号：US07733990B2
公开(公告)日：2010-06-08
申请号：US11503412
申请日：2006-08-11
申请人： Pietro Capretta
发明人： Pietro Capretta
IPC分类号： H03D1/00
CPC分类号： H03H17/0621 , H03H17/0685
摘要： A receive path in a receiver including circuitry for deriving a first stream of first digitized samples from a received analog signal at a first sampling rate, and at least one interpolating filter in parallel with the first stream of first digitized samples for generating at least a second stream of digitized samples at the first sampling rate but offset with respect to the first stream by a fraction of a sample time period.
摘要翻译：一种接收机中的接收路径，包括用于从第一采样率的接收的模拟信号导出第一数字化样本的第一流的电路和与第一数字化样本的第一流并行的至少一个内插滤波器，用于产生至少第二以第一采样率的数字化样本流，但相对于第一流偏移一小部分采样时间段。

2. 发明申请

US20090265483A1 DIRECT MEMORY ACCESS FOR ADVANCED HIGH SPEED BUS 有权
标题翻译：用于高级高速总线的直接存储器访问
公开(公告)号：US20090265483A1
公开(公告)日：2009-10-22
申请号：US12484027
申请日：2009-06-12
申请人： Rudolph Alexandre
发明人： Rudolph Alexandre
IPC分类号： G06F13/28 , G06F13/00 , G06F13/36 , G06F13/362
CPC分类号： G06F13/161 , G06F13/1684 , G06F13/28
摘要： A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.
摘要翻译：用于诸如AHB总线的主从型总线的存储器系统具有存储器，总线接口以允许存储器从总线访问，以及直接存储器访问接口，以允许来自DMA控制器的存储器访问而不占用总线。该系统可以减少总线的占用，它可以允许专用的DMA访问协议比使用总线协议更快，并且可以消除或减少对总线仲裁及相关电路和延迟的需求。仲裁器可以在存储器访问之间仲裁并给予DMA访问优先级。

3. 发明申请

US20090116437A1 COEXISTENCE OF WIRELESS PERSONAL AREA NETWORK AND WIRELESS LOCAL AREA NETWORK 有权
标题翻译：无线个人网络和无线局域网的共存
公开(公告)号：US20090116437A1
公开(公告)日：2009-05-07
申请号：US12244778
申请日：2008-10-03
申请人： Rudolph Alexandre , Wouter Aerts , Martin Ryder , Viktor Belokonskiy
发明人： Rudolph Alexandre , Wouter Aerts , Martin Ryder , Viktor Belokonskiy
IPC分类号： H04W72/04
CPC分类号： H04W48/18 , H04W88/06
摘要： Wireless transceiver apparatus for operating in a part of the RF spectrum which is shared with a co-located second wireless transceiver apparatus. The first wireless transceiver apparatus includes, a wireless transceiver unit; an arbitration interface for interfacing with an arbitration entity which arbitrates access to the shared part of the RF spectrum between the first wireless transceiver apparatus and the second wireless transceiver apparatus; wherein the arbitration interface is adapted to signal time periods when the wireless transceiver unit is operational, or requests to be operational; and wherein the arbitration interface is adapted to signal data about and commands to the first wireless transceiver apparatus during other time periods. An enhanced arbitration entity is adapted to automatically detect and switch between two modes or interference reduction, e.g. a first interference reduction means such as AFH, a second interference reduction means such as PTA. The arbitration entity gets the information of the first wireless transceiver via the arbitration interface.
摘要翻译：用于在与共同位置的第二无线收发器装置共享的RF频谱的一部分中操作的无线收发器装置。第一无线收发器装置包括：无线收发器单元; 仲裁接口，用于与仲裁实体进行接口，仲裁实体仲裁对第一无线收发器设备和第二无线收发器设备之间的RF频谱的共享部分的访问; 其中所述仲裁接口适于在所述无线收发器单元运行时或者要求运行时发出信号; 并且其中所述仲裁接口适于在其他时间段期间向所述第一无线收发器装置发送关于信号和命令的数据。增强的仲裁实体适于自动检测和切换两种模式或减少干扰，例如。诸如AFH的第一干扰减少装置，诸如PTA的第二干扰减少装置。仲裁实体通过仲裁接口获取第一个无线收发器的信息。

4. 发明申请

US20090086711A1 CORRELATION OF ACCESS CODE FOR BLUETOOTH SYNCHRONIZATION 有权
标题翻译：蓝牙同步访问代码的相关性
公开(公告)号：US20090086711A1
公开(公告)日：2009-04-02
申请号：US11863865
申请日：2007-09-28
申请人： Pietro Capretta , Viktor Belokonskiy , Alberto Gozzi
发明人： Pietro Capretta , Viktor Belokonskiy , Alberto Gozzi
IPC分类号： H04J3/06
CPC分类号： H04L7/042
摘要： A circuit for processing a packet based signal received over a Bluetooth radio link has a correlator to detect at least part of the access code. A correlator controller, reconfigures the correlator according to a timing of the access code, to detect at least part of the EDR synchronization sequence, and a demodulator demodulates the payload according to the detection. The correlator has an input signal register, a buffer for a sequence of at least part of the wanted signal values, and a series of comparators arranged to compare input signal values with corresponding ones of the wanted signal values at more than one offset. By such dual use of the same correlator, the receiver can be made more cost effective.
摘要翻译：用于处理通过蓝牙无线电链路接收的基于分组的信号的电路具有检测至少部分访问码的相关器。相关器控制器根据接入码的定时重新配置相关器，以检测至少部分EDR同步序列，并且解调器根据检测来解调有效载荷。相关器具有输入信号寄存器，用于至少部分有用信号值的序列的缓冲器，以及一系列比较器，其布置成在多于一个偏移处将输入信号值与有用信号值中的对应信号值进行比较。通过相同相关器的这种双重使用，可以使接收器更具成本效益。

5. 发明申请

US20070037511A1 Enhanced data rate receiver 有权
标题翻译：增强数据速率接收机
公开(公告)号：US20070037511A1
公开(公告)日：2007-02-15
申请号：US11503415
申请日：2006-08-11
申请人： Pietro Capretta
发明人： Pietro Capretta
IPC分类号： H04H1/00
CPC分类号： H03H17/0621 , H03H17/0685
摘要： A receiver having circuitry for generating first digitized samples from a received analog signal at a first sampling rate, e.g. an ADC. An interpolating filter is used to generate second digitized samples which are estimates of samples obtainable by sampling the received analog signal at a second sample rate lower than the first sampling rate, second digitized samples being output at the first sampling rate and including at least one unusable sample. A circuit is provided for generating a signal for controlling components of the receive path downstream of the interpolation filter to prevent processing of the unusable second digitized samples.
摘要翻译：一种接收机，具有用于以第一采样率从接收的模拟信号产生第一数字化采样的电路，例如，一个ADC。内插滤波器用于产生第二数字化采样，其是通过以低于第一采样率的第二采样率对接收的模拟信号进行采样而获得的采样的估计，第二数字化样本以第一采样率输出并且包括至少一个不可用样品。提供电路，用于产生用于控制内插滤波器下游的接收路径的分量的信号，以防止不可用的第二数字化采样的处理。

6. 发明申请

US20080111590A1 Buffer for driving capacitive load 有权
标题翻译：用于驱动容性负载的缓冲器
公开(公告)号：US20080111590A1
公开(公告)日：2008-05-15
申请号：US11599178
申请日：2006-11-14
申请人： Steven Terryn
发明人： Steven Terryn
IPC分类号： H03K3/00
CPC分类号： H03F3/3022 , H03F1/02 , H03F1/0205 , H03F2200/297 , H03F2200/336
摘要： A buffer circuit buffers incoming signals, from a local oscillator generator to a mixing circuit and has a push-pull circuit having two inputs, a first being coupled to a first incoming signal, and a second of the inputs being coupled to one of the buffered versions of the incoming signals, having a phase related to that of the first incoming signal. By coupling a second input to a buffered version rather than to the incoming signal, the load presented to the preceding circuit can be halved, while maintaining reduced power consumption. By using as a second input, a signal which is phase related to the first incoming signal, the normal operation of the push-pull circuit can be maintained. The incoming signals from the LO generator can be differential IQ signals and the buffered version of the further incoming signal be in phase with the first incoming signal.
摘要翻译：缓冲电路缓冲从本地振荡器发生器到混合电路的输入信号，并具有具有两个输入的推挽电路，第一个耦合到第一输入信号，第二个输入耦合到缓冲的输入信号的版本，具有与第一输入信号相关的相位。通过将第二输入耦合到缓冲版本而不是输入信号，呈现给先前电路的负载可以减少一半，同时保持降低的功耗。通过使用与第一输入信号相关的信号作为第二输入，可以保持推挽电路的正常操作。来自LO发生器的输入信号可以是差分IQ信号，并且进一步输入信号的缓冲版本与第一输入信号同相。

7. 发明申请

US20070036247A1 Receiver with frequency offset compensation for M-state phase modulation 有权
标题翻译：具有频率偏移补偿的接收机，用于M态相位调制
公开(公告)号：US20070036247A1
公开(公告)日：2007-02-15
申请号：US11503406
申请日：2006-08-11
申请人： Pietro Capretta , Steven Terryn , Jean-Jacques Schmit
发明人： Pietro Capretta , Steven Terryn , Jean-Jacques Schmit
IPC分类号： H04L27/06 , H04B1/10
CPC分类号： H04L27/22 , H04L2027/0065 , H04L2027/0095
摘要： Method and apparatus for a wireless receiver are described which derive at least a first stream of first digitized samples from a received analog signal at a first sampling rate and identify a first frequency offset based on a plurality of parallel correlations using complex reference signals which differ from each other by phase offsets. A second frequency offset is identified based on tracking a demodulation accuracy for each symbol which is demodulated from the first stream of digitized samples. These frequency offsets can be used to rotate decision areas in the demodulator. The methods and apparatus may be used in a Bluetooth receiver.
摘要翻译：描述了用于无线接收机的方法和装置，其以第一采样率从接收到的模拟信号中导出至少第一数字化采样的第一流，并且使用复数参考信号来识别基于多个并行相关的第一频率偏移相互偏移。基于从第一数字化样本流解调的每个符号跟踪解调精度来识别第二频率偏移。这些频率偏移可用于旋转解调器中的判定区域。方法和装置可以用在蓝牙接收机中。

8. 发明授权

US07460587B2 Electronic circuit for performing fractional time domain interpolation and related devices and methods 有权
$Electronic circuit for performing fractional time domain interpolation and related devices and methods$
标题翻译：用于执行分数时域插值的电子电路及相关设备和方法
公开(公告)号：US07460587B2
公开(公告)日：2008-12-02
申请号：US10745948
申请日：2003-12-24
申请人： Fabio Pisoni
发明人： Fabio Pisoni
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L27/2662 , H04L27/2657
摘要： A clock offset compensation arrangement may include a fractional interpolator for applying a trigonometric interpolation to a sampled input signal according to a clock offset signal. It uses transform-based processing in the frequency domain. Compared to a polynomial type interpolation it may be easier to implement, and may achieve a closer approximation to an ideal interpolation. It may reduce the effects of non-linear type errors introduced by truncation of higher powers. The arrangement may be applied to receivers or transmitters of multi-carrier modems, as well as other applications which use rate adaptation or synchronization.
摘要翻译：时钟偏移补偿装置可以包括用于根据时钟偏移信号对采样的输入信号应用三角插值的分数内插器。它在频域中使用基于变换的处理。与多项式类型插值相比，它可能更容易实现，并且可以实现更接近于理想插值的近似。它可以减少由截断较高功率引入的非线性类型误差的影响。该布置可以应用于多载波调制解调器的接收机或发射机，以及使用速率适配或同步的其他应用。

9. 发明申请

US20080100373A1 Bandwidth calibration of active filter 有权
标题翻译：有源滤波器的带宽校准
公开(公告)号：US20080100373A1
公开(公告)日：2008-05-01
申请号：US11588107
申请日：2006-10-26
申请人： Steven Terryn , Dieter Joos
发明人： Steven Terryn , Dieter Joos
IPC分类号： H03K5/00
CPC分类号： H03F1/08 , H03F3/45475 , H03F2200/264 , H03F2203/45048 , H03F2203/45138 , H03F2203/45526 , H03H11/1291
摘要： An active RC filter has an op-amp and a biasing circuit arranged to bias the op-amp to set a gain bandwidth product of the op-amp according to a desired pole frequency of the filter. The biasing circuit is operable according to an output of an RC calibration circuit. The op-amp can be an OTA transconductance amplifier, and the biasing circuit can be arranged to maintain a constant product of R and transconductance at an input of the transconductance amplifier. This biasing can help to set the pole frequency more accurately and can thus reduce the need for bandwidth margin to be provided to allow for manufacturing process variations.
摘要翻译：有源RC滤波器具有运算放大器和偏置电路，其被布置为偏置运算放大器以根据滤波器的期望极点频率设置运算放大器的增益带宽乘积。偏置电路可根据RC校准电路的输出进行操作。运算放大器可以是OTA跨导放大器，并且偏置电路可以被布置成在跨导放大器的输入处保持R和跨导的恒定乘积。该偏置可以有助于更精确地设置极点频率，从而可以减少为提供制造工艺变化而需要提供的带宽余量。

10. 发明申请

US20070037510A1 Receiver with improved sample granularity 有权
标题翻译：接收器具有改进的样品粒度
公开(公告)号：US20070037510A1
公开(公告)日：2007-02-15
申请号：US11503412
申请日：2006-08-11
申请人： Pietro Capretta
发明人： Pietro Capretta
IPC分类号： H04H1/00
CPC分类号： H03H17/0621 , H03H17/0685
摘要： A receive path in a receiver including circuitry for deriving a first stream of first digitized samples from a received analog signal at a first sampling rate, and at least one interpolating filter in parallel with the first stream of first digitized samples for generating at least a second stream of digitized samples at the first sampling rate but offset with respect to the first stream by a fraction of a sample time period.
摘要翻译：一种接收机中的接收路径，包括用于从第一采样率的接收的模拟信号导出第一数字化样本的第一流的电路和与第一数字化样本的第一流并行的至少一个内插滤波器，用于产生至少第二以第一采样率的数字化样本流，但相对于第一流偏移一小部分采样时间段。

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