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1. 发明申请

US20030079167A1 Combinational test pattern generation method and apparatus 失效
公开(公告)号：US20030079167A1
公开(公告)日：2003-04-24
申请号：US10262271
申请日：2002-10-01
申请人： NEC Electronics, Inc.
发明人： Wern-Yan Koe
IPC分类号： G06F011/00
CPC分类号： G11B20/1816 , G01R31/318371
摘要： A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization scan chain test pattern.

2. 发明授权

US6167252A Security for a mobile or personal communications device having an identification code 失效
标题翻译：具有识别码的移动或个人通信设备的安全性
公开(公告)号：US6167252A
公开(公告)日：2000-12-26
申请号：US703497
申请日：1996-08-27
申请人： Paul E. Cohen
发明人： Paul E. Cohen
IPC分类号： H04W88/02 , H04M11/00
CPC分类号： H04W12/12 , H04W12/02 , H04W88/02
摘要： A device that broadcasts an electronic serial number, or ESN, is made secure from cloning using one or more of a plurality of measures, including coupling the memory used for storing the ESN more closely to the ESN processor, fabricating the ESN memory as part of the ESN processor, including the ESN memory in another processor and encrypting communications between the other processor and the ESN processor, and comparing multiple copies of the ESN stored in different memories. The later technique is also effective in securing the JTAG port of an ESN processor.
摘要翻译：广播电子序列号或ESN的设备使用多种措施中的一种或多种进行克隆安全，包括将用于存储ESN的存储器更紧密地耦合到ESN处理器，制造ESN存储器作为 ESN处理器，包括另一处理器中的ESN存储器，并且加密另一个处理器与ESN处理器之间的通信，以及比较存储在不同存储器中的ESN的多个拷贝。后来的技术在保护ESN处理器的JTAG端口方面也是有效的。

3. 发明授权

US6081869A Bit-field peripheral 失效
标题翻译：位域外设
公开(公告)号：US6081869A
公开(公告)日：2000-06-27
申请号：US907066
申请日：1997-08-06
申请人： Paul E. Cohen
发明人： Paul E. Cohen
IPC分类号： G06F12/04 , G06F9/305 , G06F9/308 , G06F9/30
CPC分类号： G06F9/30018
摘要： A bit field system is disclosed which includes a processor as well as a bit field peripheral device which is accessed via dedicated bit field addresses. Such a system efficiently executes bit field operations. Additionally, such a system advantageously provides a processor which does not include an original bit field instruction set with the ability of performing bit field operations. Such a system also advantageously avoids difficulties involved in encoding bit field instructions.
摘要翻译：公开了一种位域系统，其包括处理器以及通过专用位域地址访问的位域外围设备。这样的系统有效地执行位字段操作。此外，这样的系统有利地提供一种处理器，其不包括具有执行位字段操作的能力的原始位字段指令集。这种系统还有利地避免了编码比特字段指令所涉及的困难。

4. 发明授权

US5748470A Semiconductor processing backup system 失效
标题翻译：半导体处理备份系统
公开(公告)号：US5748470A
公开(公告)日：1998-05-05
申请号：US596785
申请日：1996-02-05
申请人： Arthur L. Hager, III , Brian E. Marchant , Shouping Chuang , Ki Duk Kim
发明人： Arthur L. Hager, III , Brian E. Marchant , Shouping Chuang , Ki Duk Kim
IPC分类号： G06F11/20 , G05B9/03 , G05B19/042 , G05B19/418 , H01L21/02 , H01L21/66 , G05B9/02
CPC分类号： H01L22/20 , G05B19/0428 , G05B19/4184 , G05B2219/24189 , G05B2219/24195 , G05B2219/31026 , G05B2219/34487 , Y02P90/14 , Y02P90/18
摘要： A manufacturing system is disclosed which includes first and second control devices as well as a communication terminal which controls communication with the control devices. The communications terminal includes an interceptor module which receives information from the manufacturing device and provides this information to the first and second control devices.
摘要翻译：公开了一种制造系统，其包括第一和第二控制装置以及控制与控制装置的通信的通信终端。通信终端包括拦截器模块，其从制造设备接收信息并将该信息提供给第一和第二控制设备。

5. 发明授权

US5529626A Spincup with a wafer backside deposition reduction apparatus 失效
标题翻译：具有晶片背面沉积减少装置的加工
公开(公告)号：US5529626A
公开(公告)日：1996-06-25
申请号：US327730
申请日：1994-10-24
申请人： David R. Stewart
发明人： David R. Stewart
IPC分类号： G03F7/16 , G03F7/30 , H01L21/00 , B05C13/00
CPC分类号： H01L21/6715 , G03F7/162 , G03F7/3021
摘要： A spincup having a wafer backside deposition reduction apparatus is used to reduce wafer backside particle deposition of materials on a wafer during processing. The spincup includes an opening for accommodating a wafer supporting chuck and a particle guard which circumscribes the chuck. The particle guard contacts the base of the spincup and circumscribes the chuck. When the chuck supports a wafer, a wafer backside region is defined between the chuck and the particle guard. The spincup further includes an exhaust channel coupled to the wafer backside region to independently exhaust the wafer backside region. In one embodiment, the exhaust channel includes an exhaust port for connecting a vacuum generator to the exhaust channel and a shroud contacting a base of the spincup and the particle guard. In another embodiment, the exhaust channel includes exhaust tubes which replace the exhaust manifold shroud and exhaust port.
摘要翻译：使用具有晶片背面沉积还原装置的复合物在处理期间减少晶片背面颗粒在晶片上的沉积。支撑件包括用于容纳晶片支撑卡盘的开口和限制卡盘的颗粒保护器。颗粒防护装置与接头的底部接触并限制卡盘。当卡盘支撑晶片时，晶片背面区域被限定在卡盘和粒子防护罩之间。所述支柱还包括耦合到所述晶片背侧区域以排放所述晶片背侧区域的排气通道。在一个实施例中，排气通道包括用于将真空发生器连接到排气通道的排气口和接触所述填料和颗粒防护件的底部的护罩。在另一个实施例中，排气通道包括排气管，其替代排气歧管罩和排气口。

6. 发明授权

US5442770A Triple port cache memory 失效
标题翻译：三端口缓存内存
公开(公告)号：US5442770A
公开(公告)日：1995-08-15
申请号：US76286
申请日：1993-06-11
申请人： Peter G. Barratt
发明人： Peter G. Barratt
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0853 , G06F12/0886
摘要： Cache memory input/output apparatus that allows transfer of a single data word and transfer of consecutive sequences of data words in a row of memory, using two independent serial ports and a random access port whose actions are controlled in part by a memory address signal. Data transferred by the serial ports are double buffered, each serial port having two independent registers; and the two registers associated with a serial port may be ganged together to transfer data sequences having word lengths from 16, or multiples thereof, up to arbitrary multiples of the length of a row of data words.
摘要翻译：高速缓冲存储器输入/输出装置，其允许使用两个独立的串行端口和随机存取端口，其一部分由存储器地址信号来控制单个数据字的传送和数据字的连续序列的数据字的传送。由串口传输的数据是双缓冲的，每个串行端口有两个独立的寄存器; 并且与串行端口相关联的两个寄存器可以组合在一起以将具有从16或其倍数的字长度的数据序列传送到一行数据字的长度的任意倍数。

7. 发明授权

US5438238A Multiple filament enhanced ion source 失效
标题翻译：多丝增强离子源
公开(公告)号：US5438238A
公开(公告)日：1995-08-01
申请号：US035337
申请日：1993-03-19
申请人： Stephen W. Toy , David V. Alexander
发明人： Stephen W. Toy , David V. Alexander
IPC分类号： H01J27/20 , H01J7/24
CPC分类号： H01J27/205 , H01J2237/31701
摘要： An improved ion source is provided with multiple filaments and wiring for selectively connecting various combinations of filaments to a current source. In one embodiment an additional filament is a spare filament which is connected to the current source when the primary filament burns out. This decreases down time due to filament replacement. In another embodiment, an additional filament operates simultaneously with a primary filament to provide a more homogenous electron cloud and to increase filament life.
摘要翻译：改进的离子源设置有多根细丝和布线，用于选择性地将长丝的各种组合连接到电流源。在一个实施例中，另外的灯丝是备用灯丝，其在初级灯丝烧坏时连接到电流源。由于灯丝更换，这减少了时间。在另一个实施方案中，另外的细丝与初级细丝同时操作以提供更均匀的电子云并增加灯丝寿命。

8. 发明授权

US5325515A Single-component memory controller utilizing asynchronous state machines 失效
标题翻译：使用异步状态机的单组件存储器控制器
公开(公告)号：US5325515A
公开(公告)日：1994-06-28
申请号：US699823
申请日：1991-05-14
申请人： David H. Cobbs
发明人： David H. Cobbs
IPC分类号： G11C8/18 , G06F1/04
CPC分类号： G11C8/18
摘要： An asynchronous memory controller comprises plurality of flip-flops connected in a series. The input of the first flip-flop receives a signal indicating the start of a bus cycle. The input of each succeeding flip-flop in the series is connected to the output of the preceding flip-flop. The odd-numbered flip-flops in the series are activated by a first state of a clock pulse; the even-numbered flip-flops in the series are activated by a second state of a clock pulse. Each flip-flop responds to a level of the clock pulse rather than a rising or falling edge.
摘要翻译：异步存储器控制器包括串联连接的多个触发器。第一触发器的输入接收指示总线周期开始的信号。串联中的每个后续触发器的输入连接到先前触发器的输出。串联的奇数触发器由时钟脉冲的第一状态激活; 串联的偶数触发器由时钟脉冲的第二状态激活。每个触发器响应时钟脉冲的电平而不是上升沿或下降沿。

9. 发明授权

US5949820A Method for optimizing an equalization and receive filter 失效
标题翻译：优化均衡和接收滤波器的方法
公开(公告)号：US5949820A
公开(公告)日：1999-09-07
申请号：US690950
申请日：1996-08-01
申请人： Shih-Ming Shih , Hemant K. Thapar
发明人： Shih-Ming Shih , Hemant K. Thapar
IPC分类号： G05F3/22 , G11B5/00 , G11B5/035 , G11B20/10 , G11B20/18 , G11B33/14 , H03F1/30 , H03H11/04 , H03H11/12 , H03H11/50 , H03H21/00 , H03H7/30
CPC分类号： G11B20/10055 , G05F3/225 , G11B20/10009 , G11B20/10481 , H03H11/1291 , H03H21/0001 , G11B2005/001 , G11B33/14 , G11B5/035 , H03H21/0012
摘要： Apparatus and Methods are disclosed for adaptively optimizing an ER filter in a readback system of a storage device, such as a disk drive. A sample value is read from the storage device and an error measure is calculated between the sample value and an ideal value. Pole parameters and zeros of the ER filter are modified to minimize the ER filter. The apparatus and methods disclosed can function with customer data to adaptively optimize the ER filter in real time during normal operation of the storage device. Furthermore, temperature compensation circuits are disclosed to compensate for temperature dependencies in the ER filter.
摘要翻译：公开了用于在诸如磁盘驱动器的存储设备的回读系统中自适应地优化ER滤波器的装置和方法。从存储设备读取样本值，并在样本值和理想值之间计算误差测量值。 ER滤波器的极参数和零点被修改以使ER滤波器最小化。所公开的装置和方法可以与客户数据一起工作，以在存储装置的正常操作期间实时自适应地优化ER滤波器。此外，公开了温度补偿电路来补偿ER滤波器中的温度依赖性。

10. 发明授权

US5914989A PRML system with reduced complexity maximum likelihood detector 失效
标题翻译： PRML系统具有降低的复杂度最大似然检测器
公开(公告)号：US5914989A
公开(公告)日：1999-06-22
申请号：US800989
申请日：1997-02-18
申请人： Hemant K. Thapar , Shih-Ming Shih , Kwok W. Yeung
发明人： Hemant K. Thapar , Shih-Ming Shih , Kwok W. Yeung
IPC分类号： G11B20/14 , G11B20/10 , G11B20/18 , H03G3/20 , H03M13/23 , H03M13/39 , H04L1/00 , H03M13/12
CPC分类号： G11B20/10009
摘要： A less complex maximum likelihood detector can be implemented in a partial response maximum likelihood (PRML) system without degrading system performance by saturating y values from a gain control loop to a smaller range before the y values are supplied to the maximum likelihood detector. A quantity "D" of a maximum likelihood detector operating in accordance with a partial response scheme has a particular relationship with respect to the maximum (ymax) of the y input values processed by the maximum likelihood detector. In some embodiments, y values from a gain control loop are saturated from a first larger range (defined by ymaxreal) to a second smaller range (defined by a value SAT) which is at least as great as the ymax of the ideal input signal (ymaxideal) for the partial response scheme. The saturated y values are provided to the maximum likelihood detector. The D of the maximum likelihood detector (given the partial response scheme and the smaller range of y values) is in a different "two to the power of an integer range" than the D would have been given the same partial response scheme but the larger range of y values.
摘要翻译：可以在部分响应最大似然（PRML）系统中实施不太复杂的最大似然检测器，而不会在将y值提供给最大似然检测器之前将y值从增益控制环饱和到更小的范围，而不降低系统性能。根据部分响应方案操作的最大似然检测器的数量“D”与由最大似然检测器处理的y个输入值的最大值（ymax）具有特定的关系。在一些实施例中，来自增益控制环路的y值从至少与理想输入信号的ymax一样大的第一较大范围（由ymaxreal定义）饱和到第二较小范围（由SAT定义） ymaxideal）用于部分响应方案。饱和的y值被提供给最大似然检测器。最大似然检测器（给定部分响应方案和y值的较小范围）的D与D给出相同的部分响应方案不同的“二到整数范围的功率”，但是较大 y值的范围。

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