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1. 发明授权

US4644325A Low voltage, single power supply operated digital analog converter 失效
标题翻译：低电压，单电源工作的数字模拟转换器
公开(公告)号：US4644325A
公开(公告)日：1987-02-17
申请号：US789604
申请日：1985-10-21
申请人： Ira Miller
发明人： Ira Miller
IPC分类号： H03M1/00 , H03M1/68
CPC分类号： H03M1/745
摘要： A digital to analog converter circuit includes a current supply for providing a plurality of output currents of substantially equal magnitudes, a subtractor circuit coupled with selective outputs of the current supply for producing a plurality of binary weighted output currents and a summing circuit which is responsive to a binary coded digital input signal for selectively summing the binary weighted output currents and the remaining equal magnitude currents to provide a representative analog output current. The converter circuit is suited to be operated from a single source of power supply and does not require resistor trimming.
摘要翻译：数模转换器电路包括用于提供大致相等幅度的多个输出电流的电流源，与电流源的选择性输出耦合以产生多个二进制加权输出电流的减法器电路，以及响应于二进制编码数字输入信号，用于选择性地将二进制加权输出电流和剩余的相等幅度电流相加以提供代表性的模拟输出电流。转换器电路适合于从单一电源供电，不需要电阻器修整。

2. 发明申请

US20030020137A1 Structure and method for fabricating semiconductor inductor and balun structures utilizing the formation of a compliant substrate 审中-公开
标题翻译：利用顺应性衬底的形成制造半导体电感器和平衡 - 不平衡转换器的结构和方法
公开(公告)号：US20030020137A1
公开(公告)日：2003-01-30
申请号：US09911542
申请日：2001-07-25
申请人： MOTORLA, INC.
发明人： Bruce Allen Bosco , Rudy M. Emrick , Steven James Franson , Nestor Javier Escalera
IPC分类号： H01L029/04
CPC分类号： H01L28/10 , H01F17/0013 , H01L21/02197 , H01L21/02381 , H01L21/02488 , H01L21/02505 , H01L21/02513 , H01L21/02521 , H01L21/31691 , H01L27/08
摘要： Various semiconductor device structures that include an inductor or balun can be formed using a semiconductor structure having a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material; and a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material, and/or other types of material such as metals and non-metals.
摘要翻译：包括电感器或平衡 - 不平衡转换器的各种半导体器件结构可以使用具有单晶硅衬底，覆盖在单晶硅衬底上的无定形氧化物材料，覆盖无定形氧化物材料的单晶钙钛矿氧化物材料的半导体结构来形成; 以及覆盖单晶钙钛矿氧化物材料的单晶化合物半导体材料和/或其它类型的材料如金属和非金属。

3. 发明授权

US5340754A Method for forming a transistor having a dynamic connection between a substrate and a channel region 失效
标题翻译：用于形成在衬底和沟道区之间具有动态连接的晶体管的方法
公开(公告)号：US5340754A
公开(公告)日：1994-08-23
申请号：US940260
申请日：1992-09-02
申请人： Keith E. Witek , Jon T. Fitch , Carlos A. Mazure
发明人： Keith E. Witek , Jon T. Fitch , Carlos A. Mazure
IPC分类号： H01L21/336 , H01L27/06 , H01L27/118 , H01L29/417 , H01L29/735 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66666 , H01L27/0688 , H01L27/11807 , H01L29/41725 , H01L29/41766 , H01L29/41775 , H01L29/735 , H01L29/7827
摘要： A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.
摘要翻译：形成具有衬底（12）的垂直升高的晶体管（10）。导电插塞区域（22）被选择性地或外延地形成以垂直地提升晶体管（10）。第一掺杂区域（16a）和第二掺杂区域（16b）各自经由侧壁触点电耦合到导电插塞区域（22）。掺杂区域（16a和16b）用于在导电插塞区域（22）内形成电流电极区域（26）。沟道区域分离电流电极（26）。栅极电介质层（28）形成为覆盖沟道区域。形成导电层（30）以覆盖栅介电层（28）。导电层（30）形成晶体管（10）的栅电极。垂直升高晶体管（10）和导电插塞区域（22）提供改进的器件隔离和改进的器件操作。

4. 发明授权

US07351065B1 Method and electronic device connector with band and angle encoding 有权
标题翻译：方法和电子设备连接器带和角度编码
公开(公告)号：US07351065B1
公开(公告)日：2008-04-01
申请号：US11690484
申请日：2007-03-23
申请人： Thomas Y. Merrell , Rachid M. Alameh , Thomas E. Gitzinger , Michael J. Slade , David R. Zeiger
发明人： Thomas Y. Merrell , Rachid M. Alameh , Thomas E. Gitzinger , Michael J. Slade , David R. Zeiger
IPC分类号： H01R39/00
CPC分类号： H01R35/04 , H04M1/05
摘要： Disclosed is a connector including two mating sleeves, at least one of which having a plurality of first conductive contacts, a second mating sleeve configured to be rotatably joined to the first mating sleeve and also configured to support circuitry. The connector may also include at least one shaft configured to join the two mating sleeves to form a hinge. The shaft may further include at least a plurality of second conductive contacts, at least some of which that form portions of rings to make intermittent contact with at least one of the first conductive contacts based on the position of the at least one shaft relative to the position of at least one of the two mating sleeves. Embodiments of the connector may include a jack style hinge configuration, a hinge and pin style configuration, a hinge without a pin style configuration, or a spring loaded bolt configuration.
摘要翻译：公开了一种连接器，其包括两个配合套筒，其中至少一个具有多个第一导电触点，第二配合套筒构造成可旋转地连接到第一配合套筒并且还被配置为支撑电路。所述连接器还可以包括至少一个轴，所述至少一个轴构造成连接所述两个配合套以形成铰链。轴可以进一步包括至少多个第二导电触点，至少一些第二导电触点形成环的一部分，以便基于至少一个轴相对于第一导电触头的位置与第一导电触点中的至少一个间断地接触两个配合套筒中的至少一个的位置。连接器的实施例可以包括千斤顶式铰链构造，铰链和销式构造，没有销式构造的铰链或弹簧加载的螺栓构造。

5. 发明授权

US5959315A Semiconductor to optical link 失效
标题翻译：半导体到光链路
公开(公告)号：US5959315A
公开(公告)日：1999-09-28
申请号：US844027
申请日：1992-03-02
申请人： Michael S. Lebby , Christopher K. Y. Chun
发明人： Michael S. Lebby , Christopher K. Y. Chun
IPC分类号： G02B6/42 , H01L33/00
CPC分类号： G02B6/4239 , G02B6/4202 , G02B6/4249
摘要： One surface of a semiconductor component attached to one surface of a header with an opposite surface of the component having an optical input/output positioned adjacent one end of an optical fiber. The component and optical fiber are fixedly attached with no strain by a curable gel with the header acting as a heat sink. Electrical contacts are made to the component by means of leads formed on the header and/or a conductive coating deposited on the optical fiber.
摘要翻译：半导体部件的一个表面附接到集管的一个表面，其中部件的相对表面具有邻近光纤的一端定位的光学输入/输出。组件和光纤通过可固化凝胶固定地附着，其中头部用作散热器。通过形成在集管上的引线和/或沉积在光纤上的导电涂层，对部件进行电接触。

6. 发明授权

US4847869A Rapid reference acquisition and phase error compensation for radio transmission of data 失效
标题翻译：数据无线电传输的快速参考采集和相位误差补偿
公开(公告)号：US4847869A
公开(公告)日：1989-07-11
申请号：US128975
申请日：1987-12-04
申请人： Gerald P. Labedz , David E. Borth
发明人： Gerald P. Labedz , David E. Borth
IPC分类号： H04L27/38 , H04B7/005 , H04B7/01 , H04B7/26
CPC分类号： H04W56/0035 , H04B7/2678 , H04W56/005
摘要： The method and apparatus for rapid phase acquisition and random radio channel phase error compensation for a TDMA QPSK receiver is disclosed. Received quadrature signals having a known synchronizing sequence transmitted on one of the vectors is correlated to a local replica of the sequence. The output correlation detection signals are held for the duration of the TDMA timeslot and multiplied by the received quadrature signals to produce two pairs of products. The mutually exclusive product pairs are summed to recover data having the random phase error compensated.

7. 发明授权

US4443932A Self-aligned oxide isolated process and device 失效
标题翻译：自对准氧化物隔离工艺及装置
公开(公告)号：US4443932A
公开(公告)日：1984-04-24
申请号：US339954
申请日：1982-01-18
申请人： Sal Mastroianni , Walter F. Krolikowski
发明人： Sal Mastroianni , Walter F. Krolikowski
IPC分类号： H01L21/76 , H01L21/31 , H01L21/311 , H01L21/331 , H01L21/762 , H01L29/73 , H01L21/316
CPC分类号： H01L21/31111 , H01L21/76205 , H01L21/76216
摘要： Improved self-aligned semiconductor devices are made using two sets of superposed pattern forming layers; a master mask layer set containing the self-aligned patterns, and a pattern selector layer set which allows different apertures in the master mask layer to be selectively re-opened so that different device regions may be sequentially formed. The master mask layer is a double layer of a first material resistant to typical device forming processes, covered by a second etch stop material. The selector layer may be a single process resistant material or a double layer. Using combinations of silicon oxide and nitride, the process is applied to the formation of silicon islands with emitters and emitter, base, and collector contacts self-aligned to each other and a surrounding oxide isolation region. Significant area and cost savings are achieved without additional masking steps or precision alignments.
摘要翻译：改进的自对准半导体器件使用两组重叠图案形成层制成; 包含自对准图案的母版掩模层，以及允许选择性地重新打开主掩模层中的不同孔径的图案选择器层组，以便顺序地形成不同的器件区域。主掩模层是耐受典型的器件形成工艺的第一材料的双层，被第二蚀刻停止材料覆盖。选择层可以是单一的耐加工材料或双层。使用氧化硅和氮化物的组合，该过程被应用于形成硅岛，发射极和发射极，基极和集电极触点彼此自对准和周围的氧化物隔离区。无需额外的屏蔽步骤或精确对准即可实现显着的面积和成本节省。

8. 外观设计

USD272245S Radio pager or similar article 失效
公开(公告)号：USD272245S
公开(公告)日：1984-01-17
申请号：US306579
申请日：1981-09-28
申请人： William J. Scheid , Richard D. Lipinski , Giovanni Jaramillo
设计人： William J. Scheid , Richard D. Lipinski , Giovanni Jaramillo

9. 发明授权

US07427562B2 Method for fabricating closed vias in a printed circuit board 失效
标题翻译：在印刷电路板中制造封闭通孔的方法
公开(公告)号：US07427562B2
公开(公告)日：2008-09-23
申请号：US11557690
申请日：2006-11-08
申请人： Jaroslaw A. Magera , Gregory J. Dunn , Kathy D. Leganski
发明人： Jaroslaw A. Magera , Gregory J. Dunn , Kathy D. Leganski
IPC分类号： H01L21/4763
CPC分类号： H05K3/427 , H05K1/115 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/0047 , H05K3/4602 , H05K3/4652 , H05K2201/0394 , H05K2201/0959 , H05K2201/0969 , H05K2201/097 , H05K2201/09845 , H05K2203/1476 , Y10T29/49165
摘要： A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.
摘要翻译：一种在多层印刷电路板中形成封闭通孔的方法。电介质层被层叠在每侧具有金属层的中心芯的一侧。第二电介质层被层压到中心芯的另一侧。已经通过部分地穿过但不完全穿透中心芯而形成中心芯上的闭合的通孔，然后通过直径小得多的孔从相对侧完成通孔，以形成完全穿透中心芯的通路从一边到另一边。然后通孔用金属电镀以基本上闭合较小的孔。闭合通孔的大约一半被定位成使得闭合孔面对一个电介质层，并且其余的封闭通孔被定位成使得闭合孔面对另一介电层。来自一个介电层的树脂填充了大约一半的封闭通孔的空腔，而另一个介电层的树脂填充了其余的封闭通孔的圆形空腔。从每个介电层迁移到封闭通孔中的树脂的总量近似相等。

10. 发明授权

US5945772A Damped resonant piezoelectric alerting device 失效
标题翻译：阻尼谐振压电报警装置
公开(公告)号：US5945772A
公开(公告)日：1999-08-31
申请号：US87309
申请日：1998-05-29
申请人： Philip P. Macnak , Thomas James Rollins
发明人： Philip P. Macnak , Thomas James Rollins
IPC分类号： B06B1/06 , G04G13/02 , H01L41/08
CPC分类号： G04G13/021 , B06B1/0603
摘要： A damped resonant piezoelectric alerting device (600) includes a motional mass (130), a damping element (136, 156) magnetically coupled to the motional mass (130) and a piezoelectric actuator (100) which is constrained to an actuator mount (132) at a first end and coupled to the motional mass (130) at a second end. The piezoelectric actuator (100) responds to a control signal (108, 110) to generate an alternating out-of-plane movement (812, 814) of the motional mass (130) at an amplitude (412, 414). The alternating out-of-plane movement (812, 814) of the motional mass (130) is transformed into tactile energy to provide a tactile alert about a resonant frequency (608). The amplitude (412, 414) of the out-of-plane movement (812, 814) of the motional mass (130) is controlled by the damping element (136, 156). The alternating out-of-plane movement (812, 814) of the motional mass (130) is also transformed into acoustic energy to provide an audible alert above the resonant frequency (608).
摘要翻译：阻尼谐振压电报警装置（600）包括运动质量块（130），磁耦合到运动质量块（130）的阻尼元件（136,156）和被限制到致动器安装件（132）的压电致动器（100））并且在第二端处耦合到运动质量块（130）。压电致动器（100）响应控制信号（108,110）以在振幅（412,414）处产生运动质量（130）的交替的平面外运动（812,814）。运动质量（130）的交替的平面外运动（812,814）被转换成触觉能量以提供关于共振频率的触觉警报（608）。运动质量（130）的平面外移动（812,814）的振幅（412,414）由阻尼元件（136,156）控制。运动质量（130）的交替的平面外运动（812,814）也被转换成声能，以在谐振频率上方提供可听见的警报（608）。

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