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1. 发明专利

JP2013501356A System in Package 有权
标题翻译：空值
公开(公告)号：JP2013501356A
公开(公告)日：2013-01-10
申请号：JP2012522911
申请日：2010-07-22
申请人：メギカ・コーポレイションMegica Corporation
发明人：リン、モウ−シウン , リー、ジン−ユアン
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/3128 , H01L23/5389 , H01L23/60 , H01L24/16 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/82 , H01L24/94 , H01L24/96 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/0251 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/13099 , H01L2224/16225 , H01L2224/24145 , H01L2224/24225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/013
摘要：キャリアの上の多層チップと多層ダミー基板と、ブラインドリにまたは完全に多層チップを貫通し、また完全に多層ダミー基板を貫通する複数の貫通ビアと、貫通ビア内の複数のメタルプラグと、多層チップ間の、メタルプラグに接続されている、複数の金属相互接続部とを備えることができるシステムインパッケージまたはマルチチップモジュールが説明されている。多層チップは、互いに接続されるか、またはメタルプラグと金属相互接続部とを通して、マザーボード、ボールグリッドアレイ（ＢＧＡ）基板、プリント配線基板、金属基板、ガラス基板、またはセラミック基板などの、外部回路または構造物に接続されうる。
【選択図】図８２
摘要翻译：描述了系统包装或多芯片模块，其可以包括载体上的多层芯片和多层虚拟衬底，多个通孔盲目或完全穿过多层芯片并完全通过多层虚拟衬底，通孔中的多个金属插头以及连接到金属插头的多层芯片之间的多个金属互连。多层芯片可以通过金属插头彼此连接或外部电路或结构，例如母板，球栅阵列（BGA）基板，印刷电路板，金属基板，玻璃基板或陶瓷基板和金属互连。

3. 发明专利

JP2012156513A Design and assembly of high-performance subsystem 审中-公开
标题翻译：高性能子系统的设计和组装
公开(公告)号：JP2012156513A
公开(公告)日：2012-08-16
申请号：JP2012034385
申请日：2012-02-20
申请人： Megica Corp , メギカ・コーポレイションMegica Corporation
发明人： MUU-SHUN RIN
IPC分类号： H01L25/065 , H01L21/822 , H01L25/07 , H01L25/18 , H01L27/04
CPC分类号： H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2924/10253 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide multiple integrated circuit chip structure for performing inter-chip communication between integrated circuit chips having structure including neither an ESD protection circuit nor an input/output circuit.SOLUTION: Multiple integrated circuit chip structure comprises an inter-chip interface circuit 360 configured to selectively connect an internal circuit of an integrated circuit so as to test an interface circuit 385, having an ESD protection circuit 387 and an input/output circuit 389, for communicating with an external test system during a test and a burn-in procedure. Multiple wiring integrated circuit chip structure comprises a first integrated circuit chip 305 attached to one or more second integrated circuit chips 310 for physically and electrically connecting integrated circuit chips mutually.
摘要翻译：要解决的问题：提供用于在不包括ESD保护电路和输入/输出电路的结构的集成电路芯片之间进行芯片间通信的多集成电路芯片结构。解决方案：多集成电路芯片结构包括芯片间接口电路360，其被配置为选择性地连接集成电路的内部电路，以便测试具有ESD保护电路387和输入/输出电路的接口电路385 389，用于在测试和烧录过程期间与外部测试系统通信。多路布线集成电路芯片结构包括附接到一个或多个第二集成电路芯片310的第一集成电路芯片305，用于相互物理和电连接集成电路芯片。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2013038444A Interconnecting structure body and forming method therefor 有权
标题翻译：互连结构体及其形成方法
公开(公告)号：JP2013038444A
公开(公告)日：2013-02-21
申请号：JP2012223435
申请日：2012-10-05
申请人： Megica Corp , メギカ・コーポレイションMegica Corporation
发明人： M S RIN
IPC分类号： H01L21/768 , H01L21/822 , H01L23/522 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a new method for forming an interconnection line.SOLUTION: A thin line interconnection part (60) is provided in a surface of a substrate (10), or in a first dielectrics layer (12), located above a semiconductor circuit (42) formed on it. A passivation layer (18) sticks to the dielectrics layer, and a second thick dielectrics layer (20) is formed on a surface of the passivation layer. A thick and wide interconnection line is formed in the second thick dielectrics layer. The first dielectrics layer may be omitted, so as to form a wide and thick interconnection network on the surface of the passivation layer which sticks to the surface of the substrate.
摘要翻译：要解决的问题：提供一种形成互连线的新方法。解决方案：在衬底（10）的表面或位于其上形成的半导体电路（42）上方的第一电介质层（12）中设置细线互连部分（60）。钝化层（18）粘附到电介质层，并且在钝化层的表面上形成第二厚电介质层（20）。在第二厚电介质层中形成厚且宽的互连线。可以省略第一电介质层，以在钝化层的表面上形成宽而厚的互连网络，其粘附到衬底的表面。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP5085829B2 Integrated circuit chip structure 有权
公开(公告)号：JP5085829B2
公开(公告)日：2012-11-28
申请号：JP2002131172
申请日：2002-05-07
申请人：メギカ・コーポレイションMegica Corporation
发明人：ムウ−シュン・リン
IPC分类号： H01L21/822 , H01L25/18 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/04
CPC分类号： H01L2224/16145 , H01L2224/16227 , H01L2224/48091 , H01L2224/48227 , H01L2924/09701 , H01L2924/15151 , H01L2924/15311 , H01L2924/15321 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a chip structure for a multiply integrated circuit which performs chip-to-chip communication in terms of the chips for an integrated circuit having a structure without an ESD protection circuit and an input/output circuit. SOLUTION: The chip structure for a multiply integrated circuit is provided with chip-to-chip interface circuits for selective connection of internal circuits in an integrated circuit for testing an interface circuit having the ESD protection circuit and the input/output circuit for establishing communication with an external testing system during a test and a burn-in process. The chip structure is also provided with a first integrated circuit chip which is attached to one or more second integrated circuit chips, so that the integrated circuit chips are physically and electrically connected with each other. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2012527127A System in Package 有权
公开(公告)号：JP2012527127A
公开(公告)日：2012-11-01
申请号：JP2012511030
申请日：2010-05-13
申请人：メギカ・コーポレイションMegica Corporation
发明人：リー、ジン−ユアン , リン、モウ−シウン
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18 , H05K3/46
CPC分类号： H01L25/0657 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L24/24 , H01L24/45 , H01L24/82 , H01L24/96 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/24145 , H01L2224/24226 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48465 , H01L2224/73204 , H01L2224/73267 , H01L2224/8203 , H01L2224/92244 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19107 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要：多層ポリマー構造内に多層チップを、多層チップ上にオンチップ金属バンプを、多層ポリマー構造内にチップ内金属バンプを、多層ポリマー構造内にパターン形成金属層を含むことができるシステムインパッケージまたはマルチチップモジュールについて説明されている。多層ポリマー構造内の多層チップは、互いに接続されるか、または外部回路に、オンチップ金属バンプ、チップ内金属バンプ、およびパターン形成金属層を通して接続することができる。システムインパッケージは、ハンダバンプ、金属バンプ、またはワイヤボンディング接合ワイヤを通して外部回路に接続されうる。
【選択図】図５２

7. 发明专利

JP5005856B2 A method of forming an inductor for high-performance integrated circuits to overlay the surface of the semiconductor substrate 有权
公开(公告)号：JP5005856B2
公开(公告)日：2012-08-22
申请号：JP2001028283
申请日：2001-02-05
申请人：メギカ・コーポレイションMegica Corporation
发明人：モウ−シウン・リン
IPC分类号： H01L21/822 , H01L27/04

8. 发明专利

JP2013232671A Manufacturing method of line device 有权
标题翻译：线装置的制造方法
公开(公告)号：JP2013232671A
公开(公告)日：2013-11-14
申请号：JP2013141588
申请日：2013-07-05
申请人： Megica Corp , メギカ・コーポレイションMegica Corporation
发明人： HAYASHI SHIGEO , CHOU CHIEN-KANG , CHEN KE-HUNG
IPC分类号： H01L21/768 , H01L21/3205 , H01L23/12 , H01L23/522
CPC分类号： H01L23/5227 , H01L21/2885 , H01L21/563 , H01L21/76801 , H01L21/76885 , H01L23/3114 , H01L23/5223 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/83 , H01L2224/0347 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05173 , H01L2224/05176 , H01L2224/05183 , H01L2224/05548 , H01L2224/05571 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/05669 , H01L2224/1147 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45164 , H01L2224/45169 , H01L2224/45173 , H01L2224/45176 , H01L2224/45183 , H01L2224/48091 , H01L2224/48463 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48664 , H01L2224/48669 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2224/48864 , H01L2224/83101 , H01L2224/83192 , H01L2924/00011 , H01L2924/00014 , H01L2924/0002 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10329 , H01L2924/12044 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H01L2924/00 , H01L2224/48869 , H01L2224/83851 , H01L2224/05552 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a line device which is to be miniaturized.SOLUTION: A first metal pole 68 and a second metal pole are arranged on a substrate. When maximum width of the first metal pole is divided by height of the first metal pole and the second metal pole, the maximum width of the first metal pole is smaller than "4". The height of the first metal pole is 20 μm to 300 μm, and distance from a center point of the first metal pole to a center point of the second metal pole is 10 μm to 250 μm. Thereby, distance between the metal poles can be reduced to 250 μm or less, and the number of pin holes can be suppressed to a target being 400 or less. Performance of IC can be effectively improved, and resistance and a load of an IC metal connection line of a low power IC element can be significantly reduced.
摘要翻译：要解决的问题：提供一种要小型化的线路装置的制造方法。解决方案：第一金属极68和第二金属极布置在基板上。当第一金属极的最大宽度除以第一金属极和第二金属极的高度时，第一金属极的最大宽度小于“4”。第一金属极的高度为20μm〜300μm，从第一金属极的中心点到第二金属极的中心点的距离为10μm〜250μm。因此，金属极之间的距离可以减小到250μm以下，并且可以将针孔的数量抑制在400以下。可以有效地提高IC的性能，并且可以显着地降低低功率IC元件的IC金属连接线的电阻和负载。

9. 发明专利

JP5335931B2 Chip package and related technologies having a power management integrated circuit 有权
公开(公告)号：JP5335931B2
公开(公告)日：2013-11-06
申请号：JP2011543655
申请日：2009-12-22
申请人：メギカ・コーポレイションMegica Corporation
发明人：リン，ムー−シウン , リー，ジン−ユアン
IPC分类号： H01L25/00 , H02M3/155
CPC分类号： H01L23/5329 , H01L23/642 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/16 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05023 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05568 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05684 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/16245 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2924/00011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01047 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , H01L2924/12044 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , Y10T307/406 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/01074 , H01L2924/04953 , H01L2924/01004
摘要： Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described.

10. 发明专利

JP2012517716A Image and optical sensor chip package 审中-公开
公开(公告)号：JP2012517716A
公开(公告)日：2012-08-02
申请号：JP2011550201
申请日：2010-02-10
申请人：メギカ・コーポレイションMegica Corporation
发明人：リー、ジン・ユアン , リン、モウ−シウン
IPC分类号： H01L27/14 , H04N5/369 , H04N5/372 , H04N5/374
CPC分类号： H01L31/0203 , H01L24/45 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/8592 , H01L2924/01015 , H01L2924/01047 , H01L2924/12042 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/20751 , H01L2924/00012
摘要： An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip.

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