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1. 发明专利

JP2006202481A 256 meg dynamic random access memory 审中-公开
标题翻译： 256 MEG动态随机存取存储器
公开(公告)号：JP2006202481A
公开(公告)日：2006-08-03
申请号：JP2006062241
申请日：2006-03-08
申请人： Micron Technology Inc , ミクロンテクノロジー,インコーポレイテッドMicron Technology,Inc.
发明人： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC分类号： G11C11/401 , G11C29/34 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/12 , G11C29/14 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a solving means for authenticating the success/failure of a test mode. SOLUTION: This memory is provided with an array of memory cells each having two storage elements, a plurality of peripheral devices for writing data in the memory cells and reading data from the memory cells, a plurality of voltage sources for generating a plurality of supply voltages to be used by the array and the peripheral device in response to an external voltage, and a test mode logic for determining whether the memory is a test mode or not. The plurality of peripheral devices include latch circuits for latching data stored in the first group of a memory element in response to a first external signal, and write permission circuits for writing the latched data in the second group of the memory element in response to a second external signal. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于认证测试模式的成功/失败的解决方案。解决方案：该存储器具有每个具有两个存储元件的存储单元阵列，用于在存储器单元中写入数据并从存储器单元读取数据的多个外围设备，用于产生多个存储单元的多个电压源用于响应于外部电压由阵列和外围设备使用的电源电压以及用于确定存储器是否是测试模式的测试模式逻辑。多个外围设备包括用于响应于第一外部信号锁存存储在存储器元件的第一组中的数据的锁存电路，以及用于响应于第二外部存储元件将锁存的数据写入存储器元件的第二组的写许可电路外部信号。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006202480A 256 meg dynamic random access memory 审中-公开
标题翻译： 256 MEG动态随机存取存储器
公开(公告)号：JP2006202480A
公开(公告)日：2006-08-03
申请号：JP2006062155
申请日：2006-03-08
申请人： Micron Technology Inc , ミクロンテクノロジー,インコーポレイテッドMicron Technology,Inc.
发明人： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC分类号： G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To solve the problem that there is an adverse influence such as noise when maximum power is not necessary if a voltage pump of a size enough to supply necessary power is arranged. SOLUTION: A voltage pump for the dynamic random access memory is provided with a variable pump for supplying power at a variable level in response to a clock signal and an enable signal generated by the dynamic random access memory, an oscillator for generating the clock signal, and a regulator for generating a first signal to control the oscillator means. The variable pump includes a plurality of first independent pump circuits, and a plurality of second independent pump circuits. Each pump includes two substantially similar pump parts cooeperatively operated in response to the clock signal. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了解决如果排列足够大的电压的电压泵，则不需要最大功率时会产生诸如噪声等不良影响的问题。解决方案：用于动态随机存取存储器的电压泵设置有可变泵，用于响应于由动态随机存取存储器产生的时钟信号和使能信号以可变电平提供功率;振荡器，用于产生时钟信号和用于产生第一信号以调节振荡器装置的调节器。可变泵包括多个第一独立泵回路和多个第二独立泵回路。每个泵包括响应于时钟信号共同操作的两个基本相似的泵部件。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006202477A 256 meg dynamic random access memory 审中-公开
标题翻译： 256 MEG动态随机存取存储器
公开(公告)号：JP2006202477A
公开(公告)日：2006-08-03
申请号：JP2006062026
申请日：2006-03-08
申请人： Micron Technology Inc , ミクロンテクノロジー,インコーポレイテッドMicron Technology,Inc.
发明人： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC分类号： G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a means for supplying a proper operation voltage to a large semiconductor memory device. SOLUTION: A method for operating the amplification part of a voltage regulator for the dynamic random access memory includes a step of operating at least one power amplifier while a memory array is operated, a step of operating at least one booster amplifier independently of a power amplifier while a voltage pump is operated, and a step of operating a standby amplifier maintained at a low current level irrespective of the operated states of the power amplifier and the booster amplifier. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于向大型半导体存储器件提供适当的操作电压的装置。解决方案：用于操作用于动态随机存取存储器的电压调节器的放大部分的方法包括在存储器阵列被操作时操作至少一个功率放大器的步骤，独立于存储器阵列操作至少一个升压放大器的步骤功率放大器，同时操作电压泵;以及操作备用放大器的步骤，保持在低电流水平，而与功率放大器和升压放大器的操作状态无关。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2006190469A 256 meg dynamic random access memory 有权
标题翻译： 256 MEG动态随机存取存储器
公开(公告)号：JP2006190469A
公开(公告)日：2006-07-20
申请号：JP2006062198
申请日：2006-03-08
申请人： Micron Technology Inc , ミクロンテクノロジー,インコーポレイテッドMicron Technology,Inc.
发明人： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC分类号： G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To cope with a problem during power-up and to perform power-up surely in the shortest time. SOLUTION: The dynamic random access memory is provided with a memory cell array, a plurality of peripheral apparatus for writing data in the memory cell and reading out data from the memory cell, a plurality of voltage sources generating a plurality of supply voltages used by the array and the plurality of peripheral sources responding to the outside voltage, and a power-up sequence circuit for controlling power-up operation for a certain voltage source among a plurality of voltage sources. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：解决上电时的问题，并在最短的时间内确保上电。解决方案：动态随机存取存储器设置有存储单元阵列，用于在存储单元中写入数据并从存储单元读出数据的多个外围设备，产生多个电源电压的多个电压源由所述阵列和所述多个外围电源响应外部电压使用的上电序列电路，以及用于控制多个电压源中的某个电压源的上电操作的上电序列电路。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2008103073A Active termination control method and system through module register 有权
标题翻译：主动终止控制方法和通过模块寄存器的系统
公开(公告)号：JP2008103073A
公开(公告)日：2008-05-01
申请号：JP2007280300
申请日：2007-10-29
申请人： Micron Technology Inc , マイクロンテクノロジー,インコーポレイテッドMicron Technology, Inc.
发明人： JANZEN JEFFERY W
IPC分类号： G11C11/4093 , G06F3/00 , G06F12/00 , G06F13/40 , G11C11/401
CPC分类号： G06F13/4086
摘要： PROBLEM TO BE SOLVED: To provide a method and an apparatus for an active termination control in a memory by a module register providing an active termination control signal to the memory. SOLUTION: The module register monitors a system command bus for read and write commands. In the case of detecting the read or write command, the module register generates the active termination control signal to the memory. The memory turns on the active termination based on information being programmed into one or more mode registers of the memory. The memory maintains the active termination in an ON state for a predetermined time based on the information being programmed into one or more mode registers of the memory. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于通过向存储器提供有效终止控制信号的模块寄存器来在存储器中进行主动终止控制的方法和装置。
解决方案：模块寄存器监视系统命令总线以进行读写命令。在检测到读或写命令的情况下，模块寄存器产生到存储器的有效终止控制信号。存储器基于被编程到存储器的一个或多个模式寄存器中的信息来打开活动终止。存储器基于正被编程到存储器的一个或多个模式寄存器中的信息将活动终止维持在ON状态达预定时间。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008010888A Film composition deposited on substrate, and its semiconductor device 审中-公开
标题翻译：基底上沉积的膜组合物及其半导体器件
公开(公告)号：JP2008010888A
公开(公告)日：2008-01-17
申请号：JP2007235523
申请日：2007-09-11
申请人： Micron Technology Inc , マイクロンテクノロジー,インコーポレイテッドMicron Technology, Inc.
发明人： SANDHU GURTEJ , DERDERIAN GARO J
IPC分类号： C23C16/30 , H01L21/285 , C23C16/44 , H01L21/28 , H01L21/283 , H01L21/316 , H01L21/365 , H01L21/768 , H01L27/10 , H01L29/51
CPC分类号： H01L21/76843 , H01L21/02164 , H01L21/0228 , H01L21/02304 , H01L21/28167 , H01L21/28562 , H01L21/31612 , H01L21/76868 , H01L29/51
摘要： PROBLEM TO BE SOLVED: To provide a film composition deposited on a substrate and its semiconductor device. SOLUTION: An initiation layer is formed by exposing a substrate to at least an adhesive material enough to be adsorbed by the material on the substrate. The initiation layer gives a first reactive region. The reactive region is made to chemically react with the first reactive material under an atomic layer deposition condition to form a second reactive region. The second reactive region is made to chemically react with a second reactive material under a process condition enough to form a reactive layer on the initiation layer. This process is repeated to form a continuous reactive layer on the initiation layer. The adhesive material comprising the initiation layer is used that does not deteriorate by atomic layer deposition method. The initiation layer forms a final film together with one or a plurality of reactive layers. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供沉积在基板上的膜组合物及其半导体器件。解决方案：通过将衬底暴露于至少足以被衬底上的材料吸附的粘合剂材料而形成起始层。起始层产生第一反应区。使反应区域在原子层沉积条件下与第一反应性材料发生化学反应以形成第二反应区域。使第二反应区域在足以在起始层上形成反应层的工艺条件下与第二反应性材料发生化学反应。重复该过程以在起始层上形成连续的反应层。使用包含起始层的粘合剂材料，其不会通过原子层沉积方法劣化。起始层与一个或多个反应层一起形成最终的膜。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007207344A Low-voltage data path and current sense amplifier 审中-公开
标题翻译：低电压数据路径和电流检测放大器
公开(公告)号：JP2007207344A
公开(公告)日：2007-08-16
申请号：JP2006024795
申请日：2006-02-01
申请人： Micron Technology Inc , マイクロンテクノロジー,インコーポレイテッドMicron Technology, Inc.
发明人： TOMISHIMA SHIGEKI
IPC分类号： G11C11/409 , G11C11/4096
CPC分类号： G11C7/062 , G11C7/1048 , G11C2207/063
摘要： PROBLEM TO BE SOLVED: To provide a data path capable of precisely and consistently detecting readout data under a low-voltage operation condition. SOLUTION: The data path 300 includes a local input/output (LIO) line 316 and a global input/output (GIO) line 350. A source follower circuit 325 includes first and second NMOS 334A, 334B having drains connected to first and second signal lines 352A, 352B of the GIO and gates connected to first and second signal lines 318A, 318B of the LIO. A third NMOS includes a source connected to the sources of the first and second NMOS, a gate connected to a reference voltage supply part, and a drain connected to a drain of a fourth NMOS. The fourth NMOS includes a gate to which a selection signal is applied and a source connected to the ground. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够在低电压操作条件下精确且一致地检测读出数据的数据路径。数据路径300包括本地输入/输出（LIO）线路316和全局输入/输出（GIO）线路350.源极跟随器电路325包括第一和第二NMOS 334A，334B，其具有连接到第一和连接到LIO的第一和第二信号线318A，318B的GIO和门的第二信号线352A，352B。第三NMOS包括连接到第一和第二NMOS的源极的源极，连接到参考电压供应部分的栅极以及连接到第四NMOS的漏极的漏极。第四NMOS包括施加选择信号的栅极和连接到地的源极。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006244695A 256 meg dynamic random access memory 审中-公开
标题翻译： 256 MEG动态随机存取存储器
公开(公告)号：JP2006244695A
公开(公告)日：2006-09-14
申请号：JP2006062110
申请日：2006-03-08
申请人： Micron Technology Inc , ミクロンテクノロジー,インコーポレイテッドMicron Technology,Inc.
发明人： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC分类号： G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To obtain the optimal chip layout under restrictions in arranging pins and to provide power supply architecture in which a device can perform appropriate operation in the shortest period of time. SOLUTION: The power supply for a dynamic random access memory is equipped with multiple array blocks and multiple pads arranged in the center of the multiple array blocks, arranged near the multiple pads and equipped with multiple voltage source for generating the supply voltage to the multiple array blocks. The multiple voltage source is equipped with a voltage regulator having multiple power amplifiers, and at least one power amplifier is related with each of the multiple array blocks. In order to attain the setup output power level, the multiple voltage sources include voltage pumps having multiple voltage pump circuits divided into multiple groups for performing either of separate or simultaneous operation. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了在布置引脚的限制下获得最佳的芯片布局，并提供设备可以在最短的时间内执行适当的操作的电源架构。解决方案：动态随机存取存储器的电源配备有多个阵列块和多个焊盘，布置在多个阵列块的中心，布置在多个焊盘附近，并配有多个电压源，用于产生电源电压多个数组块。多电压源配备有具有多个功率放大器的电压调节器，并且至少一个功率放大器与多个阵列块中的每一个相关联。为了获得设定输出功率电平，多个电压源包括具有多个电压泵电路的电压泵，该电压泵电路被分成多组，用于执行单独或同时操作。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2006228261A Negative voltage driving of digit line insulation gate 审中-公开
标题翻译：数字线绝缘门的负电压驱动
公开(公告)号：JP2006228261A
公开(公告)日：2006-08-31
申请号：JP2005037029
申请日：2005-02-15
申请人： Micron Technology Inc , ミクロンテクノロジー,インコーポレイテッドMicron Technology,Inc.
发明人： TOMISHIMA SHIGEKI
IPC分类号： G11C11/409
CPC分类号： G11C7/08 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To decrease a leakage current at the time of standby due to short circuit of a row and a column in a semiconductor memory chip. SOLUTION: In the case of a row of a memory pre-charged to negative word line voltage (VNWL), that is a word line, when a gate of an insulation (ISO) transistor connected to the short-circuited word line and digit line is held at the VNWL level by an insulation signal driven to the VNWL level during a standby state of the row of the memory, the leakage current at the time of standby passing through a P sense amplifier in the memory is almost prevented. Since the leakage current at the time of standby is decreased, whole consumption of a current Icc is decreased from supply voltage of operation voltage of a memory circuit, thereby, power consumption of the circuit at the time of standby is decreased. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了减少由于半导体存储器芯片中的行和列的短路而在待机时的漏电流。
解决方案：在将预充电到负字线电压（VNWL）的行的一行作为字线的情况下，当连接到短路字线的绝缘（ISO）晶体管的栅极并且数字线通过在存储器行的待机状态期间被驱动到VNWL电平的绝缘信号保持在VNWL电平，几乎防止通过存储器中的P读出放大器的待机时的漏电流。由于在待机时的漏电流减小，所以电流Icc的整体消耗从存储电路的工作电压的电源电压下降，从而在待机时电路的功耗降低。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2006202484A 256 meg dynamic random access memory 审中-公开
标题翻译： 256 MEG动态随机存取存储器
公开(公告)号：JP2006202484A
公开(公告)日：2006-08-03
申请号：JP2006065222
申请日：2006-03-10
申请人： Micron Technology Inc , ミクロンテクノロジー,インコーポレイテッドMicron Technology,Inc.
发明人： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/409 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To realize a high-density memory by an economical method. SOLUTION: This dynamic random memory is provided with a plurality of independent arrays constituted of memory cells and having digit lines extending therethrough, and a plurality of peripheral devices for writing/reading data in the memory cells. The peripheral device is provided with a plurality of sense amplifiers for sensing signals on the digit lines. The sense amplifier is provided with a plurality of peripheral devices controlled by a control signal larger than a data signal written in the memory cell, a power source for generating a plurality of supply voltages, and a power distribution bus for supplying the plurality of supply voltages to the plurality of independent arrays and the peripheral devices. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过经济的方法实现高密度存储器。解决方案：该动态随机存储器设置有由存储单元构成的多个独立阵列，并且具有穿过其中的数字线，以及用于在存储单元中写入/读取数据的多个外围设备。外围设备设置有用于感测数字线上的信号的多个读出放大器。感测放大器设置有多个外围设备，其由大于写入存储单元中的数据信号的控制信号控制，用于产生多个电源电压的电源以及用于提供多个电源电压的配电总线到多个独立阵列和外围设备。版权所有（C）2006，JPO＆NCIPI

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