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    • 3. 发明授权
    • Nanoporous carbon tunable resistor/transistor and methods of production thereof
    • 纳米多孔碳可调谐电阻/晶体管及其生产方法
    • US08703523B1
    • 2014-04-22
    • US13311468
    • 2011-12-05
    • Juergen BienerTheodore F. BaumannSubho DasguptaHorst Hahn
    • Juergen BienerTheodore F. BaumannSubho DasguptaHorst Hahn
    • H01L21/00
    • H01L29/66037H01L29/0665H01L29/0673H01L29/16H01L29/1606H01L29/772
    • In one embodiment, a tunable resistor/transistor includes a porous material that is electrically coupled between a source electrode and a drain electrode, wherein the porous material acts as an active channel, an electrolyte solution saturating the active channel, the electrolyte solution being adapted for altering an electrical resistance of the active channel based on an applied electrochemical potential, wherein the active channel comprises nanoporous carbon arranged in a three-dimensional structure. In another embodiment, a method for forming the tunable resistor/transistor includes forming a source electrode, forming a drain electrode, and forming a monolithic nanoporous carbon material that acts as an active channel and selectively couples the source electrode to the drain electrode electrically. In any embodiment, the electrolyte solution saturating the nanoporous carbon active channel is adapted for altering an electrical resistance of the nanoporous carbon active channel based on an applied electrochemical potential.
    • 在一个实施例中,可调电阻器/晶体管包括电耦合在源电极和漏电极之间的多孔材料,其中多孔材料用作有源沟道,饱和有源沟道的电解质溶液,电解质溶液适于 基于施加的电化学电位改变活性通道的电阻,其中活性通道包括以三维结构排列的纳米多孔碳。 在另一个实施例中,形成可调谐电阻/晶体管的方法包括形成源电极,形成漏电极,以及形成用作有源沟道的整体式纳米多孔碳材料,并将源极电极选择性地耦合到漏电极。 在任何实施方案中,饱和纳米多孔碳活性通道的电解质溶液适于基于所施加的电化学电位来改变纳米多孔碳活性通道的电阻。
    • 5. 发明申请
    • RECONFIGURABLE PROCESSOR ARCHITECTURE
    • 可重构的处理器架构
    • US20120331268A1
    • 2012-12-27
    • US13582485
    • 2011-02-28
    • Ralf KonigTimo StripfJurgen Becker
    • Ralf KonigTimo StripfJurgen Becker
    • G06F15/80
    • G06F15/7867G06F15/8007
    • A reconfigurable data processor architecture. The processor architecture includes: a first plurality of data processing elements, each having a respective synchronization unit, a data link structure adapted for dynamically interconnecting a number of the data processing elements, at least one configuration register, and at least one control unit in operative connection with the configuration register for controlling a contents thereof, wherein, based on the contents, the first plurality of data processing elements is adapted for temporarily constituting at runtime at least one group of one or more of said data processing elements from said first plurality of data processing elements dynamically via the data link structure. The synchronization units are adapted for synchronizing data processing by individual data processing elements within the group. The first plurality of data processing elements may be reconfigurably grouped and thus adapted to various data processing tasks at runtime. This increases data processing efficiency.
    • 可重构数据处理器架构。 处理器架构包括:第一多个数据处理元件,每个数据处理元件各自具有相应的同步单元,数据链路结构,适于动态地互连多个数据处理元件,至少一个配置寄存器和至少一个操作的控制单元 与用于控制其内容的配置寄存器的连接,其中,基于内容,第一多个数据处理元件适于在运行时临时构成来自所述第一多个数据处理元件的至少一组一个或多个所述数据处理元件 数据处理元素通过数据链接结构动态地进行。 同步单元适于使组内的各个数据处理元件的数据处理同步。 第一多个数据处理元件可以被可重构地分组,并因此适用于运行时的各种数据处理任务。 这提高了数据处理效率。