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1. 发明专利

JP5404999B2 Power supply method for an integrated circuit, a system and the integrated circuit used therein 有权
公开(公告)号：JP5404999B2
公开(公告)日：2014-02-05
申请号：JP2006536202
申请日：2004-10-18
申请人：インベンサス、コーポレーションInvensas Corporation
发明人：エマニュエル、アリー
IPC分类号： H01L21/822 , G05F1/10 , G05F1/46 , G05F1/565 , G05F1/569 , G05F1/571 , G06F1/26 , G06F1/28 , H01L27/04
CPC分类号： G06F1/26

2. 发明专利

JP5076133B2 Integrated circuit with a flash 有权
公开(公告)号：JP5076133B2
公开(公告)日：2012-11-21
申请号：JP2002506443
申请日：2001-06-20
申请人：インベンサス、コーポレーションInvensas Corporation
发明人：ハンス‐ヨアヒム、ゲルケ , ステファン、コーク , ステファン、ガピッシュ
IPC分类号： G06F12/00 , G06F12/04 , G06F12/08 , G06F13/36 , G06F13/40
CPC分类号： G06F13/4018
摘要： This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion. These intermediate storage registers (4), together with an additional tag register (5), may serve as cache for the microprocessor's data requests, further increasing the potential speed of the IC.

3. 发明专利

JP5693546B2 集積回路への電力供給方法、システム及びそれに使用される集積回路有权
标题翻译：一种用于集成电路中，一种系统和集成电路其中使用电力供给方法
公开(公告)号：JP5693546B2
公开(公告)日：2015-04-01
申请号：JP2012248758
申请日：2012-11-12
申请人：インベンサス、コーポレーション , INVENSAS CORPORATION
发明人：エマニュエル、アリー
IPC分类号： H01L27/04 , G05F1/10 , H01L21/822
CPC分类号： G06F1/26

4. 发明专利

JP2013070071A Method and system for powering integrated circuit, and integrated circuit used therein 有权
标题翻译：集成电路供电方法与系统及其集成电路
公开(公告)号：JP2013070071A
公开(公告)日：2013-04-18
申请号：JP2012248758
申请日：2012-11-12
申请人： Invensas Corp , インベンサス、コーポレーションInvensas Corporation
发明人： EMMANUEL ALIE
IPC分类号： H01L21/822 , G05F1/10 , G05F1/46 , G05F1/565 , G05F1/569 , G05F1/571 , G06F1/26 , H01L27/04
CPC分类号： G06F1/26
摘要： PROBLEM TO BE SOLVED: To provide a powering method which enables a voltage supplied to a semiconductor chip to increase beyond a nominal maximum operating voltage.SOLUTION: A method for powering an integrated circuit 2 comprising within a package assembly a chip 4 comprising a plurality of logic circuits 16 each having at least one power input operated with a power voltage not exceeding a predetermined maximum operating voltage comprises the steps of: determining a first power voltage at a power input of a selected logic circuit among the logic circuits on the basis of directly measuring a second power voltage at a sensing point 61 placed within the chip at the power input of the one of the logic circuits and on the basis of the voltage drop between the sensing point and the power input of the selected one of the logic circuits; and regulating the first power voltage to a reference voltage having a value to be regulated to the predetermined maximum operating voltage in the selected one of the logic circuits.
摘要翻译：要解决的问题：提供使提供给半导体芯片的电压增加超过标称最大工作电压的供电方法。解决方案：一种用于为集成电路2供电的方法，包括在封装组件内，包括多个逻辑电路16的芯片4，每个逻辑电路具有以不超过预定最大工作电压的电源电压操作的至少一个电源输入，包括步骤基于在逻辑电路中的一个逻辑电路的功率输入处直接测量放置在芯片内的感测点61处的第二电源电压，确定逻辑电路中所选逻辑电路的功率输入处的第一电源电压并且基于感测点和所选逻辑电路的功率输入之间的电压降; 以及将所述第一电源电压调节为具有被调节到所选逻辑电路中的预定最大工作电压的值的参考电压。版权所有（C）2013，JPO＆INPIT

5. 发明申请

WO2020117336A1 CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES 审中-公开
公开(公告)号：WO2020117336A1
公开(公告)日：2020-06-11
申请号：PCT/US2019/048530
申请日：2019-08-28
申请人： INVENSAS CORPORATION
发明人： HABA, Belgacem , SITARAM, Arkalgud R.
IPC分类号： H01L25/065 , H01L25/00 , H01L23/00 , H01L21/311 , H01L21/02
摘要： Capacitive couplings in a direct- bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct- bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct- bonded together at the same bonding interface.

6. 发明申请

WO2019067579A1 INTERCONNECT STRUCTURES AND METHODS FOR FORMING SAME 审中-公开
公开(公告)号：WO2019067579A1
公开(公告)日：2019-04-04
申请号：PCT/US2018/052904
申请日：2018-09-26
申请人： INVENSAS CORPORATION
发明人： UZOH, Cyprian, Emeka , MIRKARIMI, Laura, Wills
IPC分类号： H01L21/768 , H01L21/02 , H01L21/28 , H01L21/3065
摘要： A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing.

7. 发明申请

WO2018231442A1 DEFORMABLE ELECTRICAL CONTACTS WITH CONFORMABLE TARGET PADS 审中-公开
公开(公告)号：WO2018231442A1
公开(公告)日：2018-12-20
申请号：PCT/US2018/033833
申请日：2018-05-22
申请人： INVENSAS CORPORATION
发明人： HABA, Belgacem , GUEVARA, Gabriel Z.
IPC分类号： H01L23/498
摘要： Deformable electrical contacts with conformable target pads for microelectronic assemblies and other applications are provided. A plurality of deformable electrical contacts on a first substrate may be joined to a plurality of conformable pads on a second substrate during die level or wafer level assembly of microelectronics, for example. Each deformable contact deforms to a degree that is related to the amount of joining pressure between the first substrate and the second substrate. The deformation process also wipes each respective conformable pad with the deformable electrical contact to create a fresh metal-to-metal contact for good conduction. Each conformable pad collapses as pressured by a compressible material to assume the approximate deformed shape of the electrical contact, providing a large conduction surface area, while also compensating for horizontal misalignment. Temperature can be raised to melt a dielectric, which encapsulates the electrical connections, equalizes gaps and variations between the two substrates, and permanently secures the two substrates together.

8. 发明申请

WO2018118394A1 WAFER TESTING WITHOUT DIRECT PROBING 审中-公开
公开(公告)号：WO2018118394A1
公开(公告)日：2018-06-28
申请号：PCT/US2017/064441
申请日：2017-12-04
申请人： INVENSAS CORPORATION
发明人： DELACRUZ, Javier, A. , PLANTS, William, C.
IPC分类号： G01R31/28
CPC分类号： G01R31/2856 , G01R31/2831 , G01R31/2884 , G01R31/2894
摘要： The invention pertains to in-wafer testing of integrated circuits. In particular, it pertains to apparatuses and methods for testing small integrated circuits that have pad sizes and pitches that are too small for using conventional wafer probing technology.

9. 发明申请

WO2018031457A1 WARPAGE BALANCING IN THIN PACKAGES 审中-公开
标题翻译：在薄包装中的翘曲平衡
公开(公告)号：WO2018031457A1
公开(公告)日：2018-02-15
申请号：PCT/US2017/045711
申请日：2017-08-07
申请人： INVENSAS CORPORATION
发明人： HABA, Belgacem , LEE, Sangil , MITCHELL, Craig , GUEVARA, Gabriel, Z. , DELACRUZ, Javier, A.
IPC分类号： H01L23/498 , H01L25/07 , H01L23/00
摘要： Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.
摘要翻译：器件和技术的代表性实现为载体或封装提供了强化。增强层被添加到载体的表面，通常是除了放置端子连接之外通常未充分利用的载体的底表面。加强层为载体或包装增加了结构支撑，否则可能非常薄。在各种实施例中，将增强层添加到载体或包装减少了载体或包装的翘曲。

10. 发明申请

WO2017192357A1 NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES 审中-公开
标题翻译：纳米级互连阵列堆叠模块
公开(公告)号：WO2017192357A1
公开(公告)日：2017-11-09
申请号：PCT/US2017/029881
申请日：2017-04-27
申请人： INVENSAS CORPORATION
发明人： WANG, Liang , LEE, Bongsub , HABA, Belgacem , LEE, Sangil
IPC分类号： H01L21/768
摘要： A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.
摘要翻译：提供了一种微电子组件，该微电子组件包括具有以纳米级节距阵列布置的多个纳米级导体的绝缘层和一对微电子元件。纳米级导体可以在微电子元件的触点之间形成电互连，而绝缘层可以将微电子元件机械地耦合在一起。

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