专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011079942A1 OPTIMISATION OF LOOPS AND DATA FLOW SECTIONS 审中-公开
标题翻译： LOOPS和数据流程部分的优化
公开(公告)号：WO2011079942A1
公开(公告)日：2011-07-07
申请号：PCT/EP2010/007950
申请日：2010-12-28
申请人： VORBACH, Martin , HYPERION CORE, INC.
发明人： VORBACH, Martin
IPC分类号： G06F9/45
CPC分类号： G06F15/7807 , G06F8/41 , G06F8/4441 , G06F8/452 , G06F9/3885
摘要： The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
摘要翻译：本发明涉及一种用于编译多核处理器的代码的方法，包括：检测和优化循环，将循环划分成可执行并可在物理硬件上映射的分区，具有最佳指令级并行性，优化循环迭代和/或循环计数器用于在硬件上进行理想映射，链接循环分区，生成表示分区执行顺序的列表。

2. 发明申请

WO2016100142A2 ADVANCED PROCESSOR ARCHITECTURE 审中-公开
标题翻译：高级处理器架构
公开(公告)号：WO2016100142A2
公开(公告)日：2016-06-23
申请号：PCT/US2015/065418
申请日：2015-12-13
申请人： HYPERION CORE INC. , VORBACH, Martin
发明人： VORBACH, Martin
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3828 , G06F9/384
摘要： The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises : 1) looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly; 2) checking for an Execution Unit (EXU) available for receiving a new instruction; and 3) issuing the instruction to the available Execution Unit and enter a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
摘要翻译：本发明涉及一种用于处理包括执行单元的布置的处理器的乱序指令的方法。本发明的方法包括：1）在寄存器定位表中查找操作数源，并设置相应发出的指令的操作数输入引用; 2）检查可用于接收新指令的执行单元（EXU）; 以及3）向可用的执行单元发出指令，并将由执行单元发出的指令寻址的结果寄存器的引用输入到寄存器定位表（RPT）中。

3. 发明申请

WO2012167933A1 TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARDWARE MODIFICATION 审中-公开
标题翻译：工具级和硬件级代码优化和相应的硬件修改
公开(公告)号：WO2012167933A1
公开(公告)日：2012-12-13
申请号：PCT/EP2012/002419
申请日：2012-06-06
申请人： HYPERION CORE INC. , VORBACH Martin
发明人： VORBACH Martin
IPC分类号： G06F17/50
CPC分类号： G06F8/443 , G06F8/4434 , G06F8/447 , G06F17/504 , G06F17/5045 , G06F17/5054
摘要： The present invention relates to a method, for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
摘要翻译：本发明涉及一种用于将高级软件代码编译成硬件的方法，将每个指令转换成相应的硬件块，并使用表示程序指针的执行控制信号来触发每个相应硬件块内的执行。

4. 发明申请

WO2012123061A9 PARALLEL MEMORY SYSTEMS 审中-公开
标题翻译：并行存储系统
公开(公告)号：WO2012123061A9
公开(公告)日：2012-11-15
申请号：PCT/EP2012000713
申请日：2012-02-17
申请人： HYPERION CORE INC , VORBACH MARTIN
发明人： VORBACH MARTIN
IPC分类号： G06F15/173 , G06F9/38 , G06F13/16
CPC分类号： G06F15/7839 , G06F8/4441 , G06F8/452 , G06F9/30043 , G06F9/3017 , G06F9/345 , G06F9/38 , G06F15/7821 , G06F2213/0038 , G11C8/16 , G11C11/412 , Y02D10/12 , Y02D10/13
摘要： The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.
摘要翻译：本发明涉及一种多核处理器存储器系统，其中提供该系统包括多核处理器与系统存储器之间的存储器通道，并且该系统至少包括与处理器核心一样多的存储器通道，每个存储器专用于处理器核心的通道，并且存储器系统在运行时将动态地专用于访问核心的存储器块相关联，访问内核经由存储器通道具有对存储体的专用访问。

5. 发明申请

WO2012123061A1 PARALLEL MEMORY SYSTEMS 审中-公开
标题翻译：并行存储器系统
公开(公告)号：WO2012123061A1
公开(公告)日：2012-09-20
申请号：PCT/EP2012/000713
申请日：2012-02-17
申请人： HYPERION CORE INC. , VORBACH, Martin
发明人： VORBACH, Martin
IPC分类号： G06F15/173 , G06F9/38 , G06F13/16
CPC分类号： G06F15/7839 , G06F8/4441 , G06F8/452 , G06F9/30043 , G06F9/3017 , G06F9/345 , G06F9/38 , G06F15/7821 , G06F2213/0038 , G11C8/16 , G11C11/412 , Y02D10/12 , Y02D10/13
摘要： The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.
摘要翻译：本发明涉及一种多核处理器存储器系统，其中提供的系统包括在多核处理器和系统存储器之间的存储器通道，并且该系统至少包括多个存储器通道作为处理器核心，每个存储器通道专用于处理器核心，并且存储器系统在运行时动态地将存储器块专用于存取核心，存取核心具有经由存储器通道对存储器组的专用存取。

6. 发明申请

WO2010142432A3 SYSTEM AND METHOD FOR A CACHE IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：用于多核处理器中缓存的系统和方法
公开(公告)号：WO2010142432A3
公开(公告)日：2011-12-22
申请号：PCT/EP2010003459
申请日：2010-06-09
申请人： VORBACH MARTIN , HYPERION CORE INC
发明人： VORBACH MARTIN
IPC分类号： G06F12/08 , G06F9/46 , G06F9/52
CPC分类号： G06F12/0815 , G06F9/526 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F12/0842 , G06F12/0893 , G06F2212/271 , G06F2212/50 , G06F2212/62 , Y02D10/13
摘要： The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
摘要翻译：本发明涉及多核处理器系统，特别是单包多核处理器系统，其包括至少两个处理器核，优选地至少四个处理器核，所述至少两个核中的每一个优选地至少四个处理器具有本地LEVEL-1缓存的多个LEVEL-1高速缓存的树通信结构，具有至少一个节点的树，优选地至少三个用于四处理器核心多核处理器的节点，以及TAG信息相关联到树中管理的数据，可用于处理数据。

7. 发明申请

WO2016100142A3 ADVANCED PROCESSOR ARCHITECTURE 审中-公开
标题翻译：先进的处理器架构
公开(公告)号：WO2016100142A3
公开(公告)日：2016-08-25
申请号：PCT/US2015065418
申请日：2015-12-13
申请人： HYPERION CORE INC , VORBACH MARTIN
发明人： VORBACH MARTIN
IPC分类号： G06F9/38
CPC分类号： G06F9/3826 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises : 1) looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly; 2) checking for an Execution Unit (EXU) available for receiving a new instruction; and 3) issuing the instruction to the available Execution Unit and enter a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
摘要翻译：本发明涉及一种用于在包括执行单元的配置的处理器上乱序处理指令的方法。本发明的方法包括：1）在寄存器定位表中查找操作数源并相应地设置要发布的指令的操作数输入参考; 2）检查可用于接收新指令的执行单元（EXU）; 和3）向可用执行单元发出指令，并将由要发布给执行单元的指令寻址的结果寄存器的引用输入到寄存器定位表（RPT）中。

8. 发明申请

WO2013098643A3 ADVANCED PROCESSOR ARCHITECTURE 审中-公开
标题翻译：高级处理器架构
公开(公告)号：WO2013098643A3
公开(公告)日：2013-09-06
申请号：PCT/IB2012002997
申请日：2012-12-17
申请人： HYPERION CORE INC
发明人： VORBACH MARTIN
IPC分类号： G06F9/38
CPC分类号： G06F9/30189 , G06F9/355 , G06F9/3885 , G06F9/3897
摘要： The present invention relates to a processor core having an execution unit comprising an arrangement of Arithmetic-Logic- Units, wherein the operation mode of the execution unit is switchable between an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic-Logic-Units such that a signal.from the register file crosses the execution unit and is receipt by the register file in one clock cycle; and wherein a pipelined operation mode of at least one of the Arithmetic-Logic-Units and the interconnection between the Arithmetic-Logic-Units such that a signal requires from the register file through the execution unit back to the register file more than one clock cycles.
摘要翻译：本发明涉及具有执行单元的处理器核心，该执行单元包括算术逻辑单元的布置，其中执行单元的操作模式可以在算术逻辑单元的异步操作和算术逻辑单元之间的互连之间切换 - 使得来自寄存器文件的信号跨越执行单元并且在一个时钟周期内由寄存器文件接收; 并且其中所述算术逻辑单元中的至少一个和所述算术逻辑单元之间的互连的流水线操作模式使得信号需要从所述寄存器文件通过所述执行单元返回所述寄存器文件多于一个时钟周期。

9. 发明申请

WO2013098643A2 ADVANCED PROCESSOR ARCHITECTURE 审中-公开
标题翻译：高级处理器架构
公开(公告)号：WO2013098643A2
公开(公告)日：2013-07-04
申请号：PCT/IB2012/002997
申请日：2012-12-17
申请人： HYPERION CORE INC.
发明人： VORBACH, Martin
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30189 , G06F9/355 , G06F9/3885 , G06F9/3897
摘要： The present invention relates to a processor core having an execution unit comprising an arrangement of Arithmetic-Logic- Units, wherein the operation mode of the execution unit is switchable between an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic- Logic-Units such that a signal.from the register file crosses the execution unit and is receipt by the register file in one clock cycle; and wherein a pipelined operation mode of at least one of the Arithmetic-Logic-Units and the interconnection between the Arithmetic-Logic-Units such that a signal requires from the register file through the execution unit back to the register file more than one clock cycles.
摘要翻译：本发明涉及具有执行单元的处理器核心，该执行单元包括算术逻辑单元的布置，其中执行单元的操作模式可以在算术逻辑单元的异步操作和算术逻辑单元之间的互连之间切换 - 使得来自寄存器文件的信号跨越执行单元并且在一个时钟周期内由寄存器文件接收; 并且其中所述算术逻辑单元中的至少一个和所述算术逻辑单元之间的互连的流水线操作模式使得信号需要从所述寄存器文件通过所述执行单元返回所述寄存器文件多于一个时钟周期。

10. 发明申请

WO2012167933A9 TOOL-LEVEL AND HARDWARE-LEVEL CODE OPTIMIZATION AND RESPECTIVE HARDWARE MODIFICATION 审中-公开
标题翻译：工具级和硬件级代码优化和相应的硬件修改
公开(公告)号：WO2012167933A9
公开(公告)日：2013-03-21
申请号：PCT/EP2012002419
申请日：2012-06-06
申请人： HYPERION CORE INC , VORBACH MARTIN
发明人： VORBACH MARTIN
IPC分类号： G06F17/50
CPC分类号： G06F8/443 , G06F8/4434 , G06F8/447 , G06F17/504 , G06F17/5045 , G06F17/5054
摘要： The present invention relates to a method, for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
摘要翻译：本发明涉及一种用于将高级软件代码编译成硬件的方法，将每个指令转换成相应的硬件块，并使用表示程序指针的执行控制信号来触发每个相应硬件块内的执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式