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1. 发明专利

DE2629311C2 未知
公开(公告)号：DE2629311C2
公开(公告)日：1987-11-19
申请号：DE2629311
申请日：1976-06-30
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： COULEUR, JOHN F., SCOTTSDALE, ARIZ., US , SCRIVER, ROBERT E., PHOENIX, ARIZ., US
IPC分类号： G06F13/12 , G06F12/10 , G06F13/10 , G06F9/36

2. 发明专利

DE2744359C2 未知
公开(公告)号：DE2744359C2
公开(公告)日：1987-09-24
申请号：DE2744359
申请日：1977-10-01
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： JOYCE, THOMAS F., BURLINGTON, MASS., US , RAGUIN, MICHEL M., MEDFORD, MASS., US
IPC分类号： G06F9/22 , G06F9/26 , G11C17/00 , G06F13/00
摘要： A method and an apparatus for improving the speed of executing instructions and reducing the microprogram memory requirements in a conventional digital computer system by eliminating a ROM address register for addressing microwords. The method or apparatus incorporates the use of a predetermined bit position in the microinstruction word which is set to a binary one when the microword is the last microword of an executing microprogram. The apparatus is responsive to the electronic representation of the binary one signal to cause the microinstruction execution sequence to branch to a predetermined location in the microprogram memory for execution of the following microinstruction; thus eliminating one ROM address register and at least one step in returning to a common address for starting the execution of another microprogram.

3. 发明专利

DE2300187C2 未知
公开(公告)号：DE2300187C2
公开(公告)日：1987-03-05
申请号：DE2300187
申请日：1973-01-03
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： MARTINO JUN., WILLIAM L., LOWELL, MASS., US
IPC分类号： G11C11/417 , G11C7/00 , G11C7/10 , G11C11/34 , G11C11/407 , G11C11/409 , G11C11/4096 , G11C11/419 , G11C11/40

4. 发明专利

DE2422470C2 未知
公开(公告)号：DE2422470C2
公开(公告)日：1987-02-05
申请号：DE2422470
申请日：1974-05-09
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： BARLOW, GEORGE J., TEWKSBURY, MASS., US , KLASHKA, JOHN A., ANDOVER, MASS., US
IPC分类号： G11B20/16 , G06F11/10 , G11B20/18 , G11B20/20 , G11B5/09

5. 发明专利

AU5805986A WORD PROCESSING COMPOSITE CHARACTER PROCESSING METHOD 未知
公开(公告)号：AU5805986A
公开(公告)日：1986-12-11
申请号：AU5805986
申请日：1986-05-29
申请人： HONEYWELL INFORMATION SYSTEMS INC
发明人： CAROSSO ROBERT M
IPC分类号： G06F3/12 , B41J2/485 , B41J2/505 , B41J3/01 , B41J25/20 , G06F17/21 , G09G1/14 , G09G5/22 , G09G5/24 , G09G5/26 , G09G5/32 , G06K15/02
摘要： A method for printing composite characters in a word processing system by multistriking two or more characters in the same character space. This method allows composite character graphics to be produced by using individual character graphics found within the character set of the output device. The method provides for the vertical and/or horizontal offsetting of the printhead between the striking of individual characters which form the composite character.

6. 发明专利

DE3114921C2 未知
公开(公告)号：DE3114921C2
公开(公告)日：1986-11-20
申请号：DE3114921
申请日：1981-04-13
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： CUSHING, DAVID E., CHELMSFORD, MASS., US , STANLEY, PHILIP E., WESTBORO, MASS., US
IPC分类号： G06F9/28 , G06F9/22 , G06F9/26 , G06F12/08 , G06F12/00 , G06F13/00 , G06F9/06
摘要： A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.

7. 发明专利

DE2400010C2 未知
公开(公告)号：DE2400010C2
公开(公告)日：1986-04-24
申请号：DE2400010
申请日：1974-01-02
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： GREENWALD, DONALD J., NASHUA, N.H., US , HOLTEY, THOMAS O., NEWTON, MASS., US
IPC分类号： G06F9/22 , G06F9/30 , G06F9/32 , G06F11/10 , G06F11/22 , G06F11/267 , G11C29/16

8. 发明专利

DE2459006C2 未知
公开(公告)号：DE2459006C2
公开(公告)日：1986-02-13
申请号：DE2459006
申请日：1974-12-13
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： BROWN, JAMES L., CHELMSFORD, MASS., US , WILDER JUN., RICHARD P., N.BILLERICA, MASS., US , KELLY, RICHARD P., NASHUA, N.H., US
IPC分类号： G06F12/10 , G06F9/355 , G06F12/02 , G06F12/06 , G06F9/36
摘要： Computer addressing hardware and a method of address development which utilizes the concept of a segment as the unit of addressability is disclosed.

9. 发明专利

DE2854485C2 未知
公开(公告)号：DE2854485C2
公开(公告)日：1986-02-06
申请号：DE2854485
申请日：1978-12-16
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： HOLTEY, THOMAS O., NEWTON LOWER FALLS, MASS., US , JOYCE, THOMAS F., BURLINGTON, MASS., US
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
摘要： A data processing system having a system bus; a plurality of system units including a main memory, a cache memory, a central processing unit (CPU) and a communications controller all connected in parallel to the system bus. The controller operates to supervise interconnection between the units via the system bus to transfer data therebetween, and the CPU includes a memory request device for generating data requests in response to the CPU. The cache memory includes a private interface connecting the CPU to the cache memory for permitting direct transmission of data requests from the CPU to the cache memory and direct transmission of requested data from the cache memory to the CPU; a cache directory and data buffer for evaluating the data requests to determine when the requested data is not present in the cache memory; and a system bus interface connecting the cache memory to the system bus for obtaining CPU requested data not found in the cache memory from the main memory via the system bus in response to the cache directory and data buffer. The cache memory may also include replacement and update apparatus for determining when the system bus is transmitting data to be written into a specific address in main memory and for replacing the data in a corresponding specific address in the cache memory with the data then on the system bus.

10. 发明专利

DE2926322C2 未知
公开(公告)号：DE2926322C2
公开(公告)日：1985-10-31
申请号：DE2926322
申请日：1979-06-29
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： NIBBY JUN., CHESTER M., PEABODY, MASS., US , PANEPINTO JUN., WILLIAM, TEWKSBURY, MASS., US
IPC分类号： G06F12/06 , G11C11/407 , G11C8/00
摘要： A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned at an initial physical row location providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board further includes a register for receiving address signals for accessing the contents of a memory location, rotating chip selection circuits which include a set of switches and an arithmetic unit having first and second sets of input terminals. The first set of input terminals is connected to the register for receiving predetermined ones of the address signals representative of the physical row location of chips being addressed and the second set of input terminals are connected to receive signals from the set of switches. The arithmetic unit operates to perform a predetermined arithmetic operation upon the signals applied to the sets of input terminals to generate a set of logical row address signals for enabling the number of chips at the initial row location.

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