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1. 发明专利

AU6549198A System and method for multi-level memory domain protection 未知
公开(公告)号：AU6549198A
公开(公告)日：1998-11-11
申请号：AU6549198
申请日：1998-03-10
申请人： HAL COMPUTER SYSTEMS INC
发明人： BHARADHWAJ RAJEEV
IPC分类号： G06F12/14
摘要： A system and method for multi-level memory domain protection. A user process for executing operating system code at a first protection level and user code at a second protection level. A domain process for executing the operating system code at the first protection level and domain code at the second protection level. The operating system code protecting the domain code, executing at the second protection level, from the user code, executing at the second protection level, by context switching between the user process context and the domain process context.

2. 发明专利

DE813713T1 未知
公开(公告)号：DE813713T1
公开(公告)日：1998-10-22
申请号：DE96909505
申请日：1996-02-29
申请人： HAL COMPUTER SYSTEMS INC
发明人： PENG LEON , LIH YOLIN , CHANG CHI-WEI
IPC分类号： G06F12/10 , G06F17/30
摘要： A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a translation for a specified input address. If exactly one valid entry of the TLB stores a translation for the specified input address then the output address corresponding to the specified input address is determined from the contents of that entry. Otherwise, the translation table is searched for a translation for the specified input address. If two or more valid entries of the TLB store a translation for the specified input address, then these entries are invalidated. If the translation table must be searched then the method involves retrieving from the translation table, and inserting into the TLB, a translation for the specified input address and possibly one or more translations for other input addresses stored with the translation for the specified input address in one node of the B-tree implementing the translation table. When a particular input address retrieved from the translation table is inserted into the TLB, it is determined whether there is exactly one valid entry in the TLB that stores a translation for the particular input address If so, then the translation retrieved from the memory is inserted into that entry, and no multiple TLB entries for the same input address are created.

3. 发明专利

DE69320503D1 未知
公开(公告)号：DE69320503D1
公开(公告)日：1998-10-01
申请号：DE69320503
申请日：1993-01-27
申请人： HAL COMPUTER SYSTEMS INC
发明人： KITAHARA TAKESHI , MONTOYE ROBERT K
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/017

4. 发明专利

AU6178098A A communications system for client-server data processing systems 未知
公开(公告)号：AU6178098A
公开(公告)日：1998-09-29
申请号：AU6178098
申请日：1998-02-19
申请人： HAL COMPUTER SYSTEMS INC
发明人： BHARADHWAJ RAJEEV
IPC分类号： G06F13/00 , G06F9/46

5. 发明专利

AU6172998A A naming system for hierarchically named computer accessible objects 未知
公开(公告)号：AU6172998A
公开(公告)日：1998-09-29
申请号：AU6172998
申请日：1998-02-19
申请人： HAL COMPUTER SYSTEMS INC
发明人： BHARADHWAJ RAJEEV
IPC分类号： G06F15/16 , G06F9/46 , G06F12/00 , G06F17/30

6. 发明专利

AU5608298A A system and method for execution management of computer programs 未知
公开(公告)号：AU5608298A
公开(公告)日：1998-07-31
申请号：AU5608298
申请日：1997-12-16
申请人： HAL COMPUTER SYSTEMS INC
发明人： BHARADHWAJ RAJEEV
IPC分类号： G06F9/46 , G06F9/50 , G06F12/10
摘要： A system for managing execution of a computer program. A domain array is used to reduce the overhead associated with managing multiple instances of a computer program. A portion of virtual address space is reserved for multiple instances of the computer program, each instance having virtual address space reserved for program code and data. The virtual addresses of the program code for the plurality of instances are mapped to shared physical address space having the executable code. The virtual addresses of data for the plurality of instances are mapped to respective dedicated portions of physical address space having data for the plurality of instances.

7. 发明专利

AT170348T 未知
公开(公告)号：AT170348T
公开(公告)日：1998-09-15
申请号：AT93101199
申请日：1993-01-27
申请人： HAL COMPUTER SYSTEMS INC
发明人： KITAHARA TAKESHI , MONTOYE ROBERT K
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/017

8. 发明专利

DE69327876T2 未知
公开(公告)号：DE69327876T2
公开(公告)日：2000-10-05
申请号：DE69327876
申请日：1993-12-23
申请人： HAL COMPUTER SYSTEMS INC
发明人： MONTOYE ROBERT K
IPC分类号： G11C15/00

9. 发明申请

WO1998029806A1 A SYSTEM AND METHOD FOR EXECUTION MANAGEMENT OF COMPUTER PROGRAMS 审中-公开
标题翻译：一种用于计算机程序执行管理的系统和方法
公开(公告)号：WO1998029806A1
公开(公告)日：1998-07-09
申请号：PCT/US1997023277
申请日：1997-12-16
申请人： HAL COMPUTER SYSTEMS, INC.
发明人： HAL COMPUTER SYSTEMS, INC. , BHARADHWAJ, Rajeev
IPC分类号： G06F09/46
CPC分类号： G06F9/5016 , G06F9/461 , G06F12/109
摘要： A system for managing execution of a computer program. A domain array is used to reduce the overhead associated with managing multiple instances of a computer program. A portion of virtual address space is reserved for multiple instances of the computer program, each instance having virtual address space reserved for program code and data. The virtual addresses of the program code for the plurality of instances are mapped to shared physical address space having the executable code. The virtual addresses of data for the plurality of instances are mapped to respective dedicated portions of physical address space having data for the plurality of instances.
摘要翻译：用于管理计算机程序的执行的系统。域数组用于减少与管理计算机程序的多个实例相关的开销。虚拟地址空间的一部分被保留用于计算机程序的多个实例，每个实例具有为程序代码和数据保留的虚拟地址空间。将多个实例的程序代码的虚拟地址映射到具有可执行代码的共享物理地址空间。将多个实例的数据的虚拟地址映射到具有多个实例的数据的物理地址空间的各个专用部分。

10. 发明申请

WO9731463A3 CROSSBAR SWITCH AND METHOD WITH REDUCED VOLTAGE SWING AND NO INTERNAL BLOCKING DATA PATH 审中-公开
标题翻译：具有降低电压摆幅和无内阻数据路径的交叉开关和方法
公开(公告)号：WO9731463A3
公开(公告)日：1997-12-04
申请号：PCT/US9702941
申请日：1997-02-20
申请人： HAL COMPUTER SYSTEMS INC
发明人： MU ALBERT , LARSON JEFFREY D
IPC分类号： H04L12/56 , H04Q3/52
CPC分类号： H04Q3/523 , H04L49/101 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/3018
摘要： A switch system and method transfer a data packet from a source data port to one or more destination data ports through a switch. The system comprises a source input buffer, a first and a second source input path, a first and a second output path and at least one crosspoint circuit. The source input buffer includes a first and a second data section. The first and the second data sections are coupled to the first and the second input paths respectively. The first and the second input paths couple through the crosspoint circuits at each intersection with the first and the second output paths. The method includes loading the data packets into data sections of an input buffer, transferring each data packet across an input path dedicated for each data section, transmitting each data packet over its input path, and switching the data from the input path to the output path based on a voltage differential. A crosspoint circuit in the switch system includes a first and a second reduced voltage swing line, a first and a second transistor circuit for each data input path and a sense amplifier for a data port. The first reduced voltage swing line is coupled to the first transistor circuit, the second reduced voltage swing line is coupled to the second transistor circuit and both reduced voltage swing lines are connected to the sense amplifier. The method of the unit comprises the steps of charging a first and a second reduced voltage swing line to a predetermined voltage, discharging the voltage from the first reduced voltage swing line, maintaining the voltage in the second voltage line, receiving a clock signal at the sense amplifier, and generating an output signal based on a voltage differential between the voltage lines.

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