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1. 发明专利

AT354828T 未知
公开(公告)号：AT354828T
公开(公告)日：2007-03-15
申请号：AT01953538
申请日：2001-07-17
申请人： ADVANCED MICRO DEVICES INC , FASL LLC
发明人： AL-SHAMMA ALI , AKAOGI TAKAO
IPC分类号： G11C16/06 , G11C15/00 , G11C15/04 , G11C16/26 , G11C29/04 , G06F11/20
摘要： A device for performing redundant reading in a flash memory is provided. The device includes arrays of regular memory cells and arrays of redundant memory cells. Some of the regular memory cells may be defective and those will have defective addresses. A regular sense amplifier will read the regular memory cells at their accessed address while at a time no later a redundant sense amplifier will read the redundant memory cells. A first array of CAM's will store the defective addresses of the defective memory cells while a second array of CAM's will store the input/output designators of the defective memory cells. Address matching circuitry will compare the accessed addresses with the defective addresses to determine whether the accessed address is defective. Before the end of the reading intervals of the sense amplifiers, decoding circuitry will decode the input/output designators of both the defective and non-defective memory cells. A multi-bit multiplexer stage will output either the contents of the regular memory cell or, if the address is defective, the contents of the redundant memory cell. The contents will be applied to the multiplexer output corresponding to the input/output designator of the memory cell.

2. 发明专利

DE112004000257T5 未知
公开(公告)号：DE112004000257T5
公开(公告)日：2006-02-23
申请号：DE112004000257
申请日：2004-02-05
申请人： FASL LLC SUNNYVALE , AZ ELECTRONIC MATERIALS JAPAN
发明人： MURAKAMI KENICHI , SASSA SUGURU , YOSHIKAWA KATSUHIRO , NISHIKAWA MASATO , KIMURA KEN , KINOSHITA YOSHIAKI
IPC分类号： G03F7/039 , C08L101/00 , C08L101/02 , G03F7/004 , G03F7/038 , H01L21/027 , H01L21/3213

3. 发明申请

WO2004019341A1 COLUMN-DECODING AND PRECHARGING IN A FLASH MEMORY DEVICE 审中-公开
标题翻译：闪存存储器件中的列解码和预处理
公开(公告)号：WO2004019341A1
公开(公告)日：2004-03-04
申请号：PCT/US2003/018450
申请日：2003-06-10
申请人： ADVANCED MICRO DEVICES, INC. , FUJITSU LIMITED , FASL LLC
发明人： YANG, Tien-Chung , SHIEH, Ming-Huei , KURIHARA, Kazuhiro , CHEN, Pau-Ling , WONG, Keith , CHUNG, Michael, S.
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C16/0458 , G11C16/0475 , G11C16/0491
摘要： Methods of reading a memory cell, and memory arrays that use these methods, are described. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are coupled to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. For precharging, an electrical load is applied to a first node in a memory array. A second node, separated from the first node by at least one intervening node in the same word line in the memory array, is precharged.
摘要翻译：描述读取存储单元的方法和使用这些方法的存储器阵列。一组存储单元被布置成具有行（X维）和列（Y维）的矩形阵列。在一行中，存储器单元的源极和漏极被耦合以形成线性链。公共字线连接到行中的每个门。单独的列线连接到链的相邻存储器单元之间的每个节点。四列Y解码器用于选择用于感测操作的列线。在感测操作期间，将电压源施加到四列中的两条线。对于预充电，电负载被施加到存储器阵列中的第一节点。通过存储器阵列中相同字线中的至少一个中间节点与第一节点分离的第二节点被预充电。

4. 发明申请

WO2003054964A3 MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE 审中-公开
公开(公告)号：WO2003054964A3
公开(公告)日：2003-07-03
申请号：PCT/US2002/039781
申请日：2002-12-11
申请人： FASL LLC
发明人： OGURA, Jusuke , RAMSBEY, Mark, T. , HALLIYAL, Arvind , KRIVOKAPIC, Zoran , NGO, Minh, Van , TRIPSAS, Nicholas, H.
IPC分类号： H01L27/115
摘要： A MONOS device and method for making the device has a charge trapping dielectric layer (32), such as an oxide-nitride-oxide (ONO) layer (34, 36, 38), formed on a substrate (30). A recess (44) is created through the ONO layer (32) and in the substrate (30). A metal silicide bit line (48) is formed in the recess (44) and bit line oxide (54) is formed on top of the metal silicide. A word line (56) is formed over the ONO layer (32) and the bit line oxide (54), and a low resistance silicide (58) is provided on top of the word line (56). The silicide (58) is formed by laser thermal annealing, for example.

5. 发明专利

GB2391985B I/O partitioning system and methodology to reduce band-to-band tunneling current during erase 未知
公开(公告)号：GB2391985B
公开(公告)日：2004-11-24
申请号：GB0324642
申请日：2001-11-14
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD , AMD , AMD INVESTMENTS INC , FASL LLC , SPANSION LLC
发明人： BAUTISTA JR EDWARD V , KURIHARA KAZUHIRO , LEE WENG FOOK , PAN FENG , SUNKAVALLI RAVI , HAMILTON DARLENE
IPC分类号： G11C16/02 , G11C16/06 , G11C16/16 , G11C16/34
摘要： A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.

6. 发明专利

AU2003245450A8 Column-decoding and precharging in a flash memory device 未知
公开(公告)号：AU2003245450A8
公开(公告)日：2004-03-11
申请号：AU2003245450
申请日：2003-06-10
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD , FASL LLC
发明人： KURIHARA KAZUHIRO , CHEN PAU-LING , WONG KEITH , CHUNG MICHAEL S , YANG TIEN-CHUNG , SHIEH MING-HUEI
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26

7. 发明专利

DE60126800D1 未知
公开(公告)号：DE60126800D1
公开(公告)日：2007-04-05
申请号：DE60126800
申请日：2001-07-17
申请人： ADVANCED MICRO DEVICES INC , FASL LLC
发明人： AL-SHAMMA ALI , AKAOGI TAKAO
IPC分类号： G06F11/20 , G11C16/06 , G11C15/00 , G11C15/04 , G11C16/26 , G11C29/04
摘要： A device for performing redundant reading in a flash memory is provided. The device includes arrays of regular memory cells and arrays of redundant memory cells. Some of the regular memory cells may be defective and those will have defective addresses. A regular sense amplifier will read the regular memory cells at their accessed address while at a time no later a redundant sense amplifier will read the redundant memory cells. A first array of CAM's will store the defective addresses of the defective memory cells while a second array of CAM's will store the input/output designators of the defective memory cells. Address matching circuitry will compare the accessed addresses with the defective addresses to determine whether the accessed address is defective. Before the end of the reading intervals of the sense amplifiers, decoding circuitry will decode the input/output designators of both the defective and non-defective memory cells. A multi-bit multiplexer stage will output either the contents of the regular memory cell or, if the address is defective, the contents of the redundant memory cell. The contents will be applied to the multiplexer output corresponding to the input/output designator of the memory cell.

8. 发明专利

AU2003225570A8 Memory manufacturing process with bitline isolation 未知
公开(公告)号：AU2003225570A8
公开(公告)日：2003-10-27
申请号：AU2003225570
申请日：2003-02-14
申请人： FUJITSU LTD , FASL LLC
发明人： LINGUNIS EMMANUIL , SHIRAIWA HIDEHIKO , SUN YU , RAMSBEY MARK T , KAMAL TAZRIEN , YANG JEAN Y
IPC分类号： H01L27/10 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.

9. 发明专利

AU2002357826A8 Monos device having buried metal silicide bit line 未知
公开(公告)号：AU2002357826A8
公开(公告)日：2003-07-09
申请号：AU2002357826
申请日：2002-12-11
申请人： FASL LLC
发明人： KRIVOKAPIC ZORAN , HALLIYAL ARVIND , OGURA JUSUKE , TRIPSAS NICHOLAS H , NGO MINH VAN , RAMSBEY MARK T
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/74 , H01L21/8246 , H01L29/788 , H01L29/792 , H01L27/115
摘要： A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.

10. 发明专利

TWI242845B 半導體記憶裝置及其製造方法 SEMICONDUCTOR MEMORY DEVICE AND THE MANUFACTURING METHOD THEREOF 失效
简体标题：半导体记忆设备及其制造方法 SEMICONDUCTOR MEMORY DEVICE AND THE MANUFACTURING METHOD THEREOF
公开(公告)号：TWI242845B
公开(公告)日：2005-11-01
申请号：TW092124063
申请日：2003-08-29
申请人：飛索股份有限公司 FASL LLC
发明人：東雅彥 MASAHIKO HIGASHI , 中村學 MANABU NAKAMURA , 世良賢太郎 KENTARO SERA , 南晴宏之 HIROYUKI NANSEI , 宇津野五大 YUKIHIRO UTSUNO , 高木英雄 HIDEO TAKAGI , 鍛治田達也 TATSUYA KAJITA
IPC分类号： H01L
CPC分类号： H01L21/0217 , H01L21/022 , H01L21/02252 , H01L21/28282 , H01L21/31155 , H01L21/3185 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/66833
摘要：本發明係藉由使用具有輻射線槽孔天線之電漿處理裝置的電漿氮化法來形成矽氮化膜，並形成以矽氧化膜包夾該矽氮化膜之構造的ONO膜之後，再以抗蝕圖案為遮罩進行離子注入，於記憶胞陣列區域形成位元線擴散層之後，再藉離子注入，以於矽氮化膜賦與晶格缺陷。藉此，可實現可在低溫條件下形成高品質之氮化膜，並且利用該氮化膜作為具有可充分因應近來細微化和高積體化要求之電荷捕獲功能之電荷捕獲膜的高可靠性半導體記憶裝置。
简体摘要：本发明系借由使用具有辐射线槽孔天线之等离子处理设备的等离子氮化法来形成硅氮化膜，并形成以硅氧化膜包夹该硅氮化膜之构造的ONO膜之后，再以抗蚀图案为遮罩进行离子注入，于记忆胞数组区域形成比特线扩散层之后，再藉离子注入，以于硅氮化膜赋与晶格缺陷。借此，可实现可在低温条件下形成高品质之氮化膜，并且利用该氮化膜作为具有可充分因应近来细微化和高积体化要求之电荷捕获功能之电荷捕获膜的高可靠性半导体记忆设备。

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