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6. 发明授权

US6127847A High-speed bipolar-to-CMOS logic converter circuit 失效
标题翻译：高速双极至CMOS逻辑转换电路
公开(公告)号：US6127847A
公开(公告)日：2000-10-03
申请号：US88380
申请日：1998-06-01
申请人： Guglielmo Sirna , Giuseppe Palmisano , Mario Paparo
发明人： Guglielmo Sirna , Giuseppe Palmisano , Mario Paparo
IPC分类号： H03K19/018 , H03K19/082
CPC分类号： H03K19/01812
摘要： A high-speed bipolar-to-CMOS logic converter circuit, including an input stage, including a differential amplifier meant to be connected to a bipolar-logic circuit portion and to be supplied by the supply voltage of the bipolar-logic portion, and an output stage, which is supplied by the voltage of a CMOS-logic circuit portion, a dynamic level shifting circuit interposed between the input stage and the output stage, the output stage being connected to the CMOS-logic circuit portion.
摘要翻译：一种包括输入级的高速双极至CMOS逻辑转换器电路，其包括将被连接到双极逻辑电路部分并由双极逻辑部分的电源电压提供的差分放大器，以及输出级，其由CMOS逻辑电路部分的电压提供，插入在输入级和输出级之间的动态电平移位电路，输出级连接到CMOS逻辑电路部分。

7. 发明授权

US6111297A MOS-technology power device integrated structure and manufacturing process thereof 失效
标题翻译： MOS技术功率器件的一体化结构及其制造工艺
公开(公告)号：US6111297A
公开(公告)日：2000-08-29
申请号：US85931
申请日：1998-05-28
申请人： Antonio Grimaldi , Antonino Schillaci
发明人： Antonio Grimaldi , Antonino Schillaci
IPC分类号： H01L21/336 , H01L23/482 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/72
CPC分类号： H01L29/66712 , H01L23/4824 , H01L29/0692 , H01L29/0696 , H01L29/1095 , H01L29/41741 , H01L29/4238 , H01L29/7802 , H01L29/0615 , H01L29/0619 , H01L29/0847 , H01L29/42368 , H01L2924/0002 , H01L2924/3011
摘要： A MOS-technology power device integrated structure includes a first plurality of elongated doped semiconductor stripes of a first conductivity type formed in a semiconductor layer of a second conductivity type, each including an elongated source region of the first conductivity type, an annular doped semiconductor region of the first conductivity type formed in the semiconductor layer and surrounding and merged with the elongated stripes, insulated gate stripes extending over the semiconductor layer between adjacent elongated stripes, a plurality of conductive gate fingers extending over and electrically connected to the insulated gate stripes, and a plurality of source metal fingers, each one extending over a respective elongated stripe and contacting the elongated stripe and the respective elongated source region, so that the source metal fingers and the conductive gate fingers are interdigitated.
摘要翻译： MOS技术功率器件集成结构包括形成在第二导电类型的半导体层中的第一导电类型的第一多个细长掺杂半导体条，每个包括第一导电类型的细长源区，环形掺杂半导体区形成在半导体层中的第一导电类型并且与细长条纹包围和合并，在相邻的细长条之间的半导体层上方延伸的绝缘栅极条，在绝缘栅极条上延伸并电连接的多个导电栅极指，以及多个源金属指，每个源金属指，每一个在相应的细长条上延伸并且接触细长条和相应的细长源区，使得源极金属指和导电栅指相互交错。

8. 发明授权

US5888889A Integrated structure pad assembly for lead bonding 失效
标题翻译：用于引线键合的集成结构焊盘组件
公开(公告)号：US5888889A
公开(公告)日：1999-03-30
申请号：US483315
申请日：1995-06-07
申请人： Ferruccio Frisina , Marcantonio Mangiagli
发明人： Ferruccio Frisina , Marcantonio Mangiagli
IPC分类号： H01L27/04 , H01L21/60 , H01L21/822 , H01L23/485 , H01L29/417 , H01L29/78 , H01L21/28 , H01L21/22
CPC分类号： H01L24/05 , H01L24/03 , H01L29/41725 , H01L29/7802 , H01L2224/04042 , H01L2224/05599 , H01L2224/05624 , H01L2224/45124 , H01L2224/48724 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091
摘要： A process for manufacturing an integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active elements of the power device are present. The chip portion has at least one second sub-portion wherein no functionally active elements of the power device are present. The top surface of the at least one second sub-portion is elevated with respect to the first sub-portion to form at least one protrusion which forms a support surface for a wire.
摘要翻译：一种制造用于引线键合到功率半导体器件芯片的集成结构焊盘组件的方法，该功率半导体器件芯片包括芯片部分，该芯片部分具有由金属化层覆盖的顶表面，该金属化层具有存在功率器件功能元件的第一子部分。芯片部分具有至少一个第二子部分，其中不存在功率器件的功能有效元件。至少一个第二子部分的顶表面相对于第一子部分升高以形成至少一个形成电线支撑表面的突起。

9. 发明授权

US5880628A High-efficiency voltage booster circuit operating at very low supply voltage 失效
标题翻译：高效率升压电路工作在非常低的电源电压
公开(公告)号：US5880628A
公开(公告)日：1999-03-09
申请号：US783226
申请日：1997-01-14
申请人： Marcello Criscione , Giuseppe Scilla
发明人： Marcello Criscione , Giuseppe Scilla
IPC分类号： H02M3/07 , G05F3/16
CPC分类号： H02M3/07
摘要： A voltage booster circuit including a pull-up capacitor connected to the supply line via a PMOS switching transistor. The other terminal of the pull-up capacitor is supplied with a pull-up voltage switching between a first value determining charging of the capacitor, and a second value higher than the first and determining pull-up of the capacitor. A negative voltage source presents an output connected to the control terminal of a switch transistor, and generates a negative voltage of a value lower than the first pull-up voltage value when charging the capacitor, so as to saturate the switch transistor and charge the capacitor to a voltage close to the supply voltage.
摘要翻译：一种升压电路，包括经由PMOS开关晶体管连接到电源线的上拉电容器。上拉电容器的另一个端子被提供在确定电容器的第一值的第一值之间的上拉电压和高于电容器的第一和确定上拉的第二值。负电压源提供连接到开关晶体管的控制端子的输出，并且在对电容器充电时产生低于第一上拉电压值的负电压，以使开关晶体管饱和并对电容器充电达到接近电源电压的电压。

10. 发明授权

US5874338A MOS-technology power device and process of making same 失效
标题翻译： MOS技术功率器件及其制作工艺
公开(公告)号：US5874338A
公开(公告)日：1999-02-23
申请号：US493149
申请日：1995-06-21
申请人： Giuseppe Ferla , Ferruccio Frisina
发明人： Giuseppe Ferla , Ferruccio Frisina
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10 , H01L29/739
CPC分类号： H01L29/66712 , H01L29/1095
摘要： A MOS-technology power device including a semiconductor material layer of a first conductivity type having a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type and a process of making same. A method of making the semiconductor device includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. Ions of the second conductivity type are implanted into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer. Ions of the first conductivity type are then implanted into the heavily doped regions to form source regions substantially aligned with the edges of the insulated gate layer.
摘要翻译：一种MOS技术的功率器件，包括具有设置在其中的体区的第一导电类型的半导体材料层。体区包括第二导电类型的重掺杂区域，第二导电类型的轻掺杂区域和第一导电类型的重掺杂区域及其制造方法。制造半导体器件的方法包括在半导体材料层的表面的部分上形成绝缘栅极层，以使半导体材料层的选定部分露出。第二导电类型的离子注入到半导体材料层的选定区域中。注入的离子热扩散以形成体区，每个体区包括基本上与绝缘栅层的边缘对准的重掺杂区，以及通过第一掺杂剂在绝缘栅层下方的横向扩散形成的轻掺杂区。然后将第一导电类型的离子注入到重掺杂区域中以形成与绝缘栅极层的边缘基本对准的源极区域。

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