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1. 发明专利

AU2002256434A1 Clock recovery circuit 未知
公开(公告)号：AU2002256434A1
公开(公告)日：2002-11-18
申请号：AU2002256434
申请日：2002-05-03
申请人： COREOPTICS INC
发明人： KUPFER THEODOR , DORSCHKY CLAUS
IPC分类号： H03L7/07 , H03L7/095 , H03L7/10 , H03L7/107 , H04L7/00 , H04L7/033 , H03K5/01
摘要： A clock recovery circuit for use with a high-speed data signal having a low signal to noise ratio is disclosed. The circuit includes a first phase locked loop circuit operating in a fast acquisition mode for acquiring the clock from a data signal, a second phase locked loop circuit for operating in a normal mode to recover the clock signal in the digital data signal once the first phase locked loop circuit has acquired the clock from the data signal, and a switch circuit responsive to switch control signals for switching between the first phase locked loop circuit and the second phase locked loop circuit after the first phase locked loop circuit has acquired the digital data signal.

2. 发明专利

GB2472082A Clock recovery for optical transmission systems 未知
公开(公告)号：GB2472082A
公开(公告)日：2011-01-26
申请号：GB0912881
申请日：2009-07-23
申请人： COREOPTICS INC
发明人： FLUDGER CHRIS
IPC分类号： H04L7/033 , H04B10/61
摘要： In a receiver for an optical communications system which corrects distortion of a received signal, a clock recovery system utilising a feedback and feedforward system is provided. The feedback loop 90 comprises a phase detector 92 and a voltage controlled oscillator (VCO) 72 for controlling the clocking frequency of an analogue to digital convertor (ADC) 36, while the feedforward loop 91 comprises the phase detector 92 and a delay element 94 for delaying the output of the distortion correction system. The feedback loop has a significantly lower bandwidth than the feedforward path. There are also provided methods of optimising tap weights and of acquiring initial tap weights for finite impulse response (FIR) filters in an equaliser 74. The receiver has particular application to clock recovery in a Dual Polarisation Quadrature Phase Shift Keying System.

3. 发明专利

GB0917978D0 Dual drive externally modulated laser 未知
公开(公告)号：GB0917978D0
公开(公告)日：2009-12-02
申请号：GB0917978
申请日：2009-10-14
申请人： COREOPTICS INC
IPC分类号： H04B10/50
摘要： A method of generating a signal in an optical transmitter comprising a directly modulated laser and an amplitude modulator for modulating the output of the laser. The method comprises the steps of applying a first modulation signal representing data to be transmitted to the current of the laser such that the output frequency of the laser is modulated, and applying a second modulation signal representing the data to be transmitted to the amplitude modulator such that the amplitude of the laser output is modulated.

4. 发明专利

GB201503768D0 Clock recovery for optical transmission systems 未知
公开(公告)号：GB201503768D0
公开(公告)日：2015-04-22
申请号：GB201503768
申请日：2009-07-23
申请人： COREOPTICS INC
IPC分类号： H04B10/61
摘要： A receiver for an optical communications system which corrects distortion of a received signal. A clock recovery system utilizing a feedback and feedforward system are provided. The feedback loop comprises a phase detector and a clock source, while the feedforward loop comprises the phase detector and a delay element for delaying the output of distortion correction system. The feedback loop has a significantly lower bandwidth than the feedforward path. There are also provided methods of optimizing tap weights and of acquiring initial tap weights.

5. 发明专利

AT352127T 未知
公开(公告)号：AT352127T
公开(公告)日：2007-02-15
申请号：AT02725899
申请日：2002-05-03
申请人： COREOPTICS INC
发明人： DORSCHKY CLAUS , KUPFER THEODOR
IPC分类号： H03L7/07 , H03L7/095 , H03L7/10 , H03L7/107 , H04L7/00 , H04L7/033 , H03L7/22 , H04L1/00
摘要： A clock recovery circuit for use with a high-speed data signal having a low signal to noise ratio is disclosed. The circuit includes a first phase locked loop circuit operating in a fast acquisition mode for acquiring the clock from a data signal, a second phase locked loop circuit for operating in a normal mode to recover the clock signal in the digital data signal once the first phase locked loop circuit has acquired the clock from the data signal, and a switch circuit responsive to switch control signals for switching between the first phase locked loop circuit and the second phase locked loop circuit after the first phase locked loop circuit has acquired the digital data signal.

6. 发明申请

WO2011045718A1 DUAL DRIVE EXTERNALLY MODULATED LASER 审中-公开
标题翻译：双驱动外部调制激光
公开(公告)号：WO2011045718A1
公开(公告)日：2011-04-21
申请号：PCT/IB2010/054558
申请日：2010-10-08
申请人： COREOPTICS INC , WHITEAWAY, James , KUPFER, Theo , RAABE, Christian
发明人： WHITEAWAY, James , KUPFER, Theo , RAABE, Christian
IPC分类号： H04B10/155
CPC分类号： H04B10/5051 , H04B10/504
摘要： A method of generating a signal in an optical transmitter comprising a directly modulated laser and an amplitude modulator for modulating the output of the laser. The method comprises the steps of applying a first modulation signal representing data to be transmitted to the current of the laser such that the output frequency of the laser is modulated, and applying a second modulation signal representing the data to be transmitted to the amplitude modulator such that the amplitude of the laser output is modulated.
摘要翻译：一种在光发射机中产生信号的方法，包括直接调制的激光器和用于调制激光器的输出的幅度调制器。该方法包括以下步骤：将表示要发送的数据的第一调制信号施加到激光器的电流，使得激光器的输出频率被调制，以及将表示待传输的数据的第二调制信号施加到幅度调制器，激光输出的幅度被调制。

7. 发明申请

WO02091649A3 CLOCK RECOVERY CIRCUIT 审中-公开
标题翻译：时钟恢复电路
公开(公告)号：WO02091649A3
公开(公告)日：2003-03-20
申请号：PCT/US0213937
申请日：2002-05-03
申请人： COREOPTICS INC
发明人： DORSCHKY CLAUS , KUPFER THEODOR
IPC分类号： H03L7/07 , H03L7/095 , H03L7/10 , H03L7/107 , H04L7/00 , H04L7/033 , H03K5/01
CPC分类号： H03L7/07 , H03L7/095 , H03L7/10 , H03L7/107 , H04L7/0004 , H04L7/033
摘要： A clock recovery circuit for use with a high-speed data signal having a low signal to noise ratio is disclosed. The circuit includes a first phase-locked loop circuit (104) operating in a fast acquisition mode for acquiring the clock from a data signal (D), a second phase locked loop circuit (102) for operating in a normal mode to recover the clock signal (Crec) in the digital data signal once the first phase locked loop circuit (104) has acquired the clock from the data signal, and a switch circuit (sw1, sw2, sw3) responsive to switch control signals for switching between the first phase locked loop circuit (104) and the second phase locked loop circuit (102) after the first phase locked loop circuit (104) has acquired the digital data signal.
摘要翻译：公开了一种与具有低信噪比的高速数据信号一起使用的时钟恢复电路。电路包括以快速获取模式操作的第一锁相环电路（104），用于从数据信号（D）获取时钟;第二锁相环电路（102），用于在正常模式下操作以恢复时钟一旦第一锁相环电路（104）从数据信号中获取时钟，数字数据信号中的信号（Crec）和响应于切换控制信号的开关电路（sw1，sw2，sw3），用于在第一相在第一锁相环电路（104）获取数字数据信号之后，锁定环电路（104）和第二锁相环电路（102）。

8. 发明专利

GB2520650A Clock recovery for optical transmission systems 未知
公开(公告)号：GB2520650A
公开(公告)日：2015-05-27
申请号：GB201503768
申请日：2009-07-23
申请人： COREOPTICS INC
发明人： FLUDGER CHRIS
IPC分类号： H04L7/033 , H04B10/61
摘要： Disclosed is a method of initially acquiring tap weights for an FIR filter used to correct distortion in an optical communications receiver. The receiver acquires and stores a series of samples 160 of a received signal. A blind optimisation algorithm 162 is then applied to the series of samples to obtain an estimate of tap weights for a Finite Impulse Response (FIR) filter of the receiver configured to equalise a received optical signal. A further embodiment, a method optimising tap weights in a FIR filter to reduce distortion in an optical receiver comprises: monitoring the tap weight centre of the filter; calculating an offset of tap weight centre from the central tap position of the FIR filter, and using the offset to define a sampling clock phase of an ADC, the output of which is passed to the FIR filter.

9. 发明专利

DE602004028021D1 VERFAHREN UND SCHALTUNG ZUR VERSTÄRKUNGSREGELUNG 未知
公开(公告)号：DE602004028021D1
公开(公告)日：2010-08-19
申请号：DE602004028021
申请日：2004-04-23
申请人： COREOPTICS INC
发明人： LANGENBACH STEFAN , STOJANOVIC NEBOJSA
IPC分类号： H03G3/30 , H03G3/00 , H03M1/18

10. 发明专利

AT473550T 未知
公开(公告)号：AT473550T
公开(公告)日：2010-07-15
申请号：AT04729098
申请日：2004-04-23
申请人： COREOPTICS INC
发明人： LANGENBACH STEFAN , STOJANOVIC NEBOJSA
IPC分类号： H03G3/30 , H03G3/00 , H03M1/18
摘要： This invention relates to a method for controlling an amplification within a receiver. The gain of a variable gain amplifier which amplifies an input signal to obtain a gain-controlled signal is set. Said gain controlled signal is analog-to-digital converted. Thereby digital words are generated. Each digital word has a value out of a plurality of possible digital values. Digital words having a value within a first and a second subset of the possible digital values are counted in order to generate a first and a second counter value. The gain is set in accordance with the first and second counter values in a fashion that all counter values are as equal as possible. Furthermore, this invention is related to a circuit to be used within a receiver for adjusting the gain of a variable gain amplifier in order to ensure a proper analog-to-digital conversion.

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