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1. 发明专利

JP2012147457A Method and system for providing high speed multi-stream mpeg processor 审中-公开
标题翻译：用于提供高速多流MPEG处理器的方法和系统
公开(公告)号：JP2012147457A
公开(公告)日：2012-08-02
申请号：JP2012046081
申请日：2012-03-02
申请人： Broadlogic Network Technologies Inc , ブロードロジックネットワークテクノロジーズインコーポレイテッド
发明人： ZHANG WEIMIN , LIO BINFAN , WANG ZHONGQIANG
IPC分类号： H04N7/32 , G06K9/36 , H01L20060101 , H04N5/00 , H04N5/272 , H04N7/12 , H04N7/26 , H04N7/30 , H04N7/50
CPC分类号： H04N21/2362 , H04N19/174 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N21/40
摘要： PROBLEM TO BE SOLVED: To provide an MPEG decoder capable of effectively handling video processing.SOLUTION: According to one aspect of an MPEG processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then read from the off-chip memory for processing. The read data is then decoded, and decoded results and associated information are stored in the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is read from the off-chip memory, provided to an analog encoder, and encoded in a format that is compatible with an analog display device.
摘要翻译：要解决的问题：提供能够有效处理视频处理的MPEG解码器。解决方案：根据MPEG处理器的一个方面，用于相应通道的多个MPEG数据流被单独存储在片外存储器中。然后从片外存储器中读出通道的对应数据进行处理。然后对读取的数据进行解码，将解码结果和相关信息存储在片外存储器中。可用于解码后续数据的部分或全部相关信息存储在片上存储器中。当需要显示视频图像时，从芯片内存中读取为此目的所需的相应数据，提供给模拟编码器，并以与模拟显示设备兼容的格式进行编码。版权所有（C）2012，JPO＆INPIT

2. 发明申请

WO2006057848A2 METHOD AND SYSTEM FOR MULTI-PROGRAM CLOCK RECOVERY AND TIMESTAMP CORRECTION 审中-公开
标题翻译：用于多程序时钟恢复和时间校正的方法和系统
公开(公告)号：WO2006057848A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/041204
申请日：2005-11-14
申请人： BROADLOGIC NETWORK TECHNOLOGIES INC. , LIU, Binfan , AYERS, Thomas , ZHANG, Weimin
发明人： LIU, Binfan , AYERS, Thomas , ZHANG, Weimin
IPC分类号： G06F1/12
CPC分类号： H04N21/4305 , H04N5/4401 , H04N21/4307
摘要： A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.
摘要翻译：解码器包括被配置为接收节目并提取嵌入在节目中的定时信息和时间戳的传输引擎。加法器被配置为将一组定时偏移量添加到定时信息组，以便从第一时间基准到第二时间基准调整定时信息。定时偏移和定时信息的和被称为映射时序信息。校正引擎被配置为在程序中遇到定时信息时更新定时偏移，并且偏移寄存器被配置为：接收定时偏移，存储定时偏移，并将定时偏移传送给加法器。加法器还被配置为将时间偏移量添加到时间戳，以便调整从第一时间到第二时间的时间戳的时间基准。程序是被配置为接收调整的时间戳以解码程序的解码器。

3. 发明申请

WO2005089479A2 METHOD AND SYSTEM FOR PROVIDING FASTER CHANNEL SWITCHING IN A DIGITAL BROADCAST SYSTEM 审中-公开
标题翻译：在数字广播系统中提供更快的频道切换的方法和系统
公开(公告)号：WO2005089479A2
公开(公告)日：2005-09-29
申请号：PCT/US2005/009078
申请日：2005-03-18
申请人： BROADLOGIC NETWORK TECHNOLOGIES, INC. , ZHANG, Weimin , LIU, Bin-Fan
发明人： ZHANG, Weimin , LIU, Bin-Fan
IPC分类号： H04B7/212 , H04H20/77 , H04J1/00 , H04L12/16 , H04L29/06 , H04N5/00 , H04N7/26 , H04N7/50 , H04Q11/00
CPC分类号： H04N5/44 , H04L29/06027 , H04L65/604 , H04L65/607 , H04N19/107 , H04N19/12 , H04N19/134 , H04N19/172 , H04N19/40 , H04N19/61 , H04N19/85 , H04N21/4331 , H04N21/434 , H04N21/4383 , H04N21/4384 , H04N21/4385 , H04N21/482 , H04Q2213/13034 , H04Q2213/13174 , H04Q2213/13248
摘要： Methods, apparatuses, and systems are presented for switching between channels of encoded media data involving receiving encoded media data including reference frames and dependent frames for a plurality of channels, wherein each dependent frame refers to at least one reference frame. Frames associated with a first channel from the plurality of channels are decoded to generate a decoded signal for the first channel. While decoding frames associated with the first channel, data corresponding to at least one reference frame associated with a second channel from the plurality of channels are stored. In response to a control signal for switching from the first to the second channel, at least one dependent frame associated with the second channel is decoded by utilizing the stored data corresponding to the at least one reference frame associated with the second channel, to generate a decoded signal for the second channel.
摘要翻译：呈现用于在编码媒体数据的信道之间切换的方法，装置和系统，所述编码媒体数据涉及接收包括用于多个信道的参考帧和相关帧的编码媒体数据，其中每个从属帧指的是至少一个参考帧。与来自多个通道的第一通道相关联的帧被解码以产生用于第一通道的解码信号。在解码与第一信道相关联的帧时，存储与来自多个信道的与第二信道相关联的至少一个参考帧的数据。响应于用于从第一信道切换到第二信道的控制信号，通过利用对应于与第二信道相关联的至少一个参考帧的所存储的数据来解码与第二信道相关联的至少一个相关帧，以产生第二通道的解码信号。

4. 发明申请

WO2005006404A2 METHOD AND SYSTEM FOR PROVIDING A HIGH SPEED MULTI-STREAM MPEG PROCESSOR 审中-公开
标题翻译：提供高速多流MPEG处理器的方法和系统
公开(公告)号：WO2005006404A2
公开(公告)日：2005-01-20
申请号：PCT/US2004/022228
申请日：2004-07-09
申请人： BROADLOGIC NETWORK TECHNOLOGIES INC. , ZHANG, Wei-Min , LIU, Binfan , WANG, Zhongqiang
发明人： ZHANG, Wei-Min , LIU, Binfan , WANG, Zhongqiang
IPC分类号： H01L
CPC分类号： H04N21/2362 , H04N19/174 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N21/40
摘要： An MPEG processor is provided. According to one aspect of the processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then retrieved from the off-chip memory for processing. The retrieved data is then decoded. The decoded results and associated information are stored on the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is then retrieved from the off-chip memory and provided to an analog encoder for encoding in a format that is compatible with an analog display device.
摘要翻译：提供MPEG处理器。根据处理器的一个方面，用于相应通道的多个MPEG数据流被单独存储在片外存储器中。然后从芯片外存储器中检索通道的相应数据进行处理。然后对所检索的数据进行解码。解码结果和相关信息存储在片外存储器中。可用于解码后续数据的部分或全部相关信息存储在片上存储器中。当需要显示视频图像时，然后从片外存储器检索所需的相应数据，并将其提供给与模拟显示装置兼容的格式的模拟编码器进行编码。

5. 发明申请

WO2004059933A1 A FULLY PARALLEL MULTI-CHANNEL DEMODULATOR 审中-公开
标题翻译：完全并行多通道解调器
公开(公告)号：WO2004059933A1
公开(公告)日：2004-07-15
申请号：PCT/US2002/041841
申请日：2002-12-30
申请人： BROADLOGIC NETWORK TECHNOLOGIES, INC.
发明人： ZHANG, WeiMin , RADIONOV, Vladimir , STENERSON, Roger , LIU, Bin-Fan , KOU, Yu
IPC分类号： H04L27/14
CPC分类号： H04H40/18 , H04L5/06
摘要： An improved multi-channel demodulator (44) is provided. The improved demodulator includes an automatic gain control (28), a data buffer (26, 30) and a demodulation engine (44). Data from various RF channels are processed by AGC in order to keep the data at their respective constant levels. Output from AGC (28) is passed to the data buffer for storage (30). Corresponding data from a selected channel is then processed by the demodulation engine (44). The improved demodulator is able to operate in any one of three operating modes, namely, a data processing mode, a channel switching mode and a waiting mode. In the data processing modes, the demodulation engine processes the channel data that is currently loaded into the demodulation engine. In the channel-switching mode, the demodulation engine stores the current channel data into the data buffer and retrieves and loads channel data from another channel for processing. In addition, status and history information relating to the current channel data is stored into a channel status memory (42) and status and history information relating to the next channel be processed is retrieved from the channel status memory (42). In one exemplary aspect, in order to reduce the channel switching time, status and history information relating to the next channel to be processed is preloaded during the previous data processing mode. In the waiting mode, the demodulation engine awaits further processing instructions to decide whether to enter into either the data processing mode or the channel-switching mode.
摘要翻译：提供改进的多通道解调器（44）。改进的解调器包括自动增益控制（28），数据缓冲器（26,30）和解调引擎（44）。来自各种RF信道的数据由AGC处理，以便将数据保持在各自的恒定水平。来自AGC（28）的输出被传递到用于存储的数据缓冲器（30）。然后由解调引擎（44）处理来自所选频道的对应数据。改进的解调器能够以三种操作模式中的任一种操作，即数据处理模式，信道切换模式和等待模式。在数据处理模式中，解调引擎处理当前加载到解调引擎中的信道数据。在通道切换模式中，解调引擎将当前通道数据存储到数据缓冲器中，并从另一个通道检索并加载通道数据进行处理。此外，从频道状态存储器（42）检索与当前频道数据有关的状态和历史信息，并将其与处理下一频道的状态和历史信息相关联。在一个示例性方面，为了减少信道切换时间，在先前的数据处理模式期间预先加载与要处理的下一个信道相关的状态和历史信息。在等待模式中，解调引擎等待进一步的处理指令来决定是进入数据处理模式还是进入信道切换模式。

6. 发明申请

WO2003026242A1 A DIGITAL IMPLEMENTATION OF MULTI-CHANNEL DEMODULATORS 审中-公开
标题翻译：多通道解调器的数字实现
公开(公告)号：WO2003026242A1
公开(公告)日：2003-03-27
申请号：PCT/US2002/029807
申请日：2002-09-18
申请人： BROADLOGIC NETWORK TECHNOLOGIES, INC.
发明人： ZHANG, Weimin , MISKO, Tim , WOODBURN, Jeremy
IPC分类号： H04L27/06
CPC分类号： H04L51/28 , G01S1/026 , G01S5/021 , G01S5/06 , G06F1/1626 , G06F1/1639 , G06F3/0481 , G06F9/465 , G06F11/1425 , G06F11/1482 , G06F11/2007 , G06F12/109 , G06F21/305 , G06F21/6209 , G06F21/74 , G06F21/88 , G06F2221/2105 , G06F2221/2115 , G09G5/363 , G11B20/10009 , G11B20/10425 , G11B20/22 , G11B27/034 , H01L27/14625 , H03L7/091 , H04B1/707 , H04B7/18582 , H04B7/2628 , H04B7/2687 , H04B10/25754 , H04J3/0655 , H04J3/0658 , H04J13/0077 , H04J13/16 , H04L1/0002 , H04L1/0015 , H04L1/0041 , H04L1/0057 , H04L1/006 , H04L1/0066 , H04L1/0068 , H04L1/0071 , H04L1/1685 , H04L1/1841 , H04L1/187 , H04L9/085 , H04L9/304 , H04L12/12 , H04L12/40117 , H04L12/417 , H04L12/462 , H04L12/4641 , H04L25/03038 , H04L25/03343 , H04L25/03866 , H04L25/4902 , H04L25/4904 , H04L25/497 , H04L27/02 , H04L27/156 , H04L27/3416 , H04L29/06 , H04L29/06027 , H04L29/12339 , H04L29/12471 , H04L41/0206 , H04L41/0213 , H04L41/042 , H04L41/046 , H04L41/06 , H04L41/0604 , H04L41/5009 , H04L41/5022 , H04L41/5035 , H04L41/5087 , H04L43/0829 , H04L43/50 , H04L45/04 , H04L45/22 , H04L45/24 , H04L47/10 , H04L47/11 , H04L47/12 , H04L47/14 , H04L47/15 , H04L47/193 , H04L47/2416 , H04L47/2433 , H04L47/27 , H04L47/283 , H04L47/34 , H04L47/70 , H04L47/72 , H04L47/745 , H04L47/765 , H04L47/822 , H04L47/824 , H04L49/90 , H04L49/9094 , H04L51/04 , H04L51/38 , H04L61/2503 , H04L61/2553 , H04L63/126 , H04L65/1006 , H04L65/1016 , H04L65/1043 , H04L65/1093 , H04L65/4061 , H04L65/4092 , H04L65/605 , H04L65/607 , H04L67/1002 , H04L67/1034 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/166 , H04L69/18 , H04L69/40 , H04L2001/0098 , H04L2012/40215 , H04L2012/40273 , H04M1/723 , H04M1/72519 , H04M1/72533 , H04M3/007 , H04M3/16 , H04M3/42221 , H04M3/4283 , H04M3/56 , H04M7/0057 , H04M7/1295 , H04M11/06 , H04M2203/2088 , H04M2203/5054 , H04N1/00957 , H04N1/031 , H04N1/0318 , H04N1/1934 , H04N1/1935 , H04N1/32106 , H04N1/40 , H04N5/04 , H04N5/073 , H04N5/126 , H04N5/2251 , H04N5/2257 , H04N5/23248 , H04N5/23254 , H04N5/23258 , H04N5/23267 , H04N5/2327 , H04N5/23277 , H04N5/272 , H04N5/38 , H04N5/4401 , H04N5/4448 , H04N5/445 , H04N5/45 , H04N5/46 , H04N5/64 , H04N5/642 , H04N5/66 , H04N5/76 , H04N5/775 , H04N5/85 , H04N5/907 , H04N7/0112 , H04N7/0122 , H04N7/163 , H04N7/17327 , H04N9/3129 , H04N9/641 , H04N9/642 , H04N9/7925 , H04N9/8042 , H04N19/109 , H04N19/115 , H04N19/139 , H04N19/152 , H04N19/174 , H04N19/19 , H04N19/194 , H04N19/51 , H04N19/517 , H04N19/527 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/91 , H04N21/234318 , H04N21/2368 , H04N21/2383 , H04N21/2543 , H04N21/2547 , H04N21/41415 , H04N21/4143 , H04N21/4181 , H04N21/42607 , H04N21/42653 , H04N21/4307 , H04N21/4312 , H04N21/4314 , H04N21/4318 , H04N21/433 , H04N21/4341 , H04N21/43622 , H04N21/43632 , H04N21/4382 , H04N21/44012 , H04N21/440218 , H04N21/4532 , H04N21/458 , H04N21/4621 , H04N21/4623 , H04N21/47211 , H04N21/6175 , H04N21/6187 , H04N21/6582 , H04N21/812 , H04N21/84 , H04N21/854 , H04N2201/0094 , H04N2201/02493 , H04N2201/03112 , H04N2201/03133 , H04N2201/03141 , H04N2201/03145 , H04N2201/03187 , H04N2201/3212 , H04N2201/3222 , H04N2201/3274 , H04Q3/0025 , H04Q3/60 , H04Q2213/1302 , H04Q2213/13039 , H04Q2213/1304 , H04Q2213/13076 , H04Q2213/13095 , H04Q2213/13109 , H04Q2213/13298 , H04Q2213/13349 , H04R1/028 , H04S7/301 , H04W4/06 , H04W4/10 , H04W4/12 , H04W4/14 , H04W8/245 , H04W8/26 , H04W8/265 , H04W12/10 , H04W24/00 , H04W28/00 , H04W28/18 , H04W28/24 , H04W28/26 , H04W36/02 , H04W40/00 , H04W40/02 , H04W48/08 , H04W52/0216 , H04W52/0225 , H04W52/0248 , H04W52/0274 , H04W52/30 , H04W56/00 , H04W64/00 , H04W68/00 , H04W72/042 , H04W72/1252 , H04W72/1268 , H04W74/008 , H04W74/0816 , H04W74/0833 , H04W76/10 , H04W76/12 , H04W76/18 , H04W76/30 , H04W76/34 , H04W76/45 , H04W80/00 , H04W84/042 , H04W84/08 , H04W84/12 , H04W88/06 , H04W88/08 , H04W88/085 , H04W88/16 , H04W92/02 , H04W92/12 , Y02D10/13 , Y02D70/168 , Y02D70/30 , Y02D70/40 , Y02D70/446 , Y02D70/449 , Y02D70/46 , Y10S370/906 , Y10S370/907 , Y10S707/99943
摘要： A method and circuitry for implementing digital multi-channel demodulation circuits (figs 2 and 6). More particularly, embodiments of the present invention provide a digital multi-channel demodulator circuit (250, 650). The demodulator includes a frequency-block down-converter (210, 610) that receives a multi-channel analog RF signal and shifts the multi-channel analog RF signal to a lower frequency band. An ADC (220, 620) receives the multi-channel analog RF signal from the frequency-block down-converter and converts the multi-channel analog RF signal to a multi-channel digital RF signal. A digital channel demultiplexer (230, 630) receives the multi-channel digital RF signal from the ADC and demultiplexes the multi-channel digital RF signal into separate digital RF channels.
摘要翻译：一种用于实现数字多通道解调电路的方法和电路（图2和图6）。更具体地，本发明的实施例提供一种数字多通道解调器电路（250,650）。解调器包括接收多通道模拟RF信号并将多通道模拟RF信号移位到较低频带的频块下变频器（210,610）。 ADC（220,620）从频块下变频器接收多通道模拟RF信号，并将多通道模拟RF信号转换为多通道数字RF信号。数字信道解复用器（230,630）从ADC接收多信道数字RF信号，并将多信道数字RF信号解复用为分立的数字RF信道。

7. 发明申请

WO2003039036A1 MULTI-CHANNEL BROADBAND CONTENT DISTRIBUTION SYSTEM 审中-公开
标题翻译：多通道宽带内容分发系统
公开(公告)号：WO2003039036A1
公开(公告)日：2003-05-08
申请号：PCT/US2002/035118
申请日：2002-10-30
申请人： BROADLOGIC NETWORK TECHNOLOGIES, INC.
发明人： FRANCESCA, Anthony , ZHANG, Weimin
IPC分类号： H04B7/216
CPC分类号： H04L5/0005 , H04L5/0064 , H04L5/06 , H04L67/32 , H04L67/34 , H04L69/14 , H04N21/23412 , H04N21/2365 , H04N21/2383 , H04N21/2385 , H04N21/2402
摘要： A system for managing bandwidth in a content distribution system is provided. The system can be incorporated into the content head end of the content distribution system. The system includes a program multiplexer, a multi-channel modulating module, a channel multiplexer, a digital-to-analog converter and a frequency block-up converter, all arranged in a sequential configuration. Packets representing respective content programs are fed to the program multiplexer. The program multiplexer multiplexes the packets into an output queue. How the packets are multiplexed by the program multiplexer into the output queue depends on the specific design and/or application. Packets from the output queue are then fed to the multi-channel modulating module. The multi-channel modulating module receives the packets and routes them to various modulators representing corresponding RF channels. The various modulators then modulate the respective packets to generate corresponding RF signals. These RF signals are then multiplexed by the channel multiplexer into a multi-channel RF signal. The multi-channel RF signal is then forwarded to the digital-to-analog converter for conversion into an analog, multi-channel RF signal. The frequency block-up converter then takes the analog multi-channel RF signal and shifts its to a higher frequency band for transmission. The shifted analog multi-channel RF signal is then transmitted over a medium to one or more customer premises equipment.
摘要翻译：提供了一种用于管理内容分发系统中的带宽的系统。该系统可以并入到内容分发系统的内容头端。该系统包括程序多路复用器，多通道调制模块，通道多路复用器，数模转换器和频率块转换器，全部以顺序配置排列。表示相应内容节目的分组被馈送到节目多路复用器。程序复用器将数据包复用到输出队列中。数据包如何被程序多路复用器复用到输出队列中取决于具体的设计和/或应用程序。然后将来自输出队列的数据包送入多通道调制模块。多通道调制模块接收分组并将它们路由到表示对应RF信道的各种调制器。然后，各种调制器调制各个分组以产生相应的RF信号。然后，这些RF信号被信道多路复用器复用成多信道RF信号。然后将多通道RF信号转发到数模转换器，以转换成模拟多通道RF信号。然后，频率块转换器接收模拟多声道RF信号并将其移动到较高频带以进行传输。然后将移位的模拟多声道RF信号通过介质传送到一个或多个客户驻地设备。

8. 发明授权

EP1579648B1 A FULLY PARALLEL MULTI-CHANNEL DEMODULATOR 有权
标题翻译： FULL并行多通道解调器
公开(公告)号：EP1579648B1
公开(公告)日：2015-05-27
申请号：EP02796143.2
申请日：2002-12-30
申请人： Broadlogic Network Technologies, Inc.
发明人： ZHANG, WeiMin , RADIONOV, Vladimir , STENERSON, Roger , LIU, Bin-Fan , KOU, Yu
IPC分类号： H04H40/18 , H04L5/06
CPC分类号： H04H40/18 , H04L5/06

9. 发明授权

EP1451948B1 MULTI-CHANNEL BROADBAND CONTENT DISTRIBUTION SYSTEM 有权
标题翻译：多通道宽带内容分发系统
公开(公告)号：EP1451948B1
公开(公告)日：2013-06-26
申请号：EP02786639.1
申请日：2002-10-30
申请人： Broadlogic Network Technologies, Inc.
发明人： FRANCESCA, Anthony , ZHANG, Weimin
IPC分类号： H04L29/08 , H04L5/06 , H04L5/00 , H04N21/2365 , H04N21/24 , H04N21/234 , H04N21/2385 , H04N21/2383
CPC分类号： H04L5/0005 , H04L5/0064 , H04L5/06 , H04L67/32 , H04L67/34 , H04L69/14 , H04N21/23412 , H04N21/2365 , H04N21/2383 , H04N21/2385 , H04N21/2402

10. 发明授权

EP1436958B1 A DIGITAL IMPLEMENTATION OF MULTI-CHANNEL DEMODULATORS 有权
标题翻译：多通道解调器的数字实现
公开(公告)号：EP1436958B1
公开(公告)日：2010-03-24
申请号：EP02759732.7
申请日：2002-09-18
申请人： Broadlogic Network Technologies, Inc.
发明人： ZHANG, Weimin , MISKO, Tim , WOODBURN, Jeremy
IPC分类号： H04L27/06 , H04L1/02
CPC分类号： H04L51/28 , G01S1/026 , G01S5/021 , G01S5/06 , G06F1/1626 , G06F1/1639 , G06F3/0481 , G06F9/465 , G06F11/1425 , G06F11/1482 , G06F11/2007 , G06F12/109 , G06F21/305 , G06F21/6209 , G06F21/74 , G06F21/88 , G06F2221/2105 , G06F2221/2115 , G09G5/363 , G11B20/10009 , G11B20/10425 , G11B20/22 , G11B27/034 , H01L27/14625 , H03L7/091 , H04B1/707 , H04B7/18582 , H04B7/2628 , H04B7/2687 , H04B10/25754 , H04J3/0655 , H04J3/0658 , H04J13/0077 , H04J13/16 , H04L1/0002 , H04L1/0015 , H04L1/0041 , H04L1/0057 , H04L1/006 , H04L1/0066 , H04L1/0068 , H04L1/0071 , H04L1/1685 , H04L1/1841 , H04L1/187 , H04L9/085 , H04L9/304 , H04L12/12 , H04L12/40117 , H04L12/417 , H04L12/462 , H04L12/4641 , H04L25/03038 , H04L25/03343 , H04L25/03866 , H04L25/4902 , H04L25/4904 , H04L25/497 , H04L27/02 , H04L27/156 , H04L27/3416 , H04L29/06 , H04L29/06027 , H04L29/12339 , H04L29/12471 , H04L41/0206 , H04L41/0213 , H04L41/042 , H04L41/046 , H04L41/06 , H04L41/0604 , H04L41/5009 , H04L41/5022 , H04L41/5035 , H04L41/5087 , H04L43/0829 , H04L43/50 , H04L45/04 , H04L45/22 , H04L45/24 , H04L47/10 , H04L47/11 , H04L47/12 , H04L47/14 , H04L47/15 , H04L47/193 , H04L47/2416 , H04L47/2433 , H04L47/27 , H04L47/283 , H04L47/34 , H04L47/70 , H04L47/72 , H04L47/745 , H04L47/765 , H04L47/822 , H04L47/824 , H04L49/90 , H04L49/9094 , H04L51/04 , H04L51/38 , H04L61/2503 , H04L61/2553 , H04L63/126 , H04L65/1006 , H04L65/1016 , H04L65/1043 , H04L65/1093 , H04L65/4061 , H04L65/4092 , H04L65/605 , H04L65/607 , H04L67/1002 , H04L67/1034 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/166 , H04L69/18 , H04L69/40 , H04L2001/0098 , H04L2012/40215 , H04L2012/40273 , H04M1/723 , H04M1/72519 , H04M1/72533 , H04M3/007 , H04M3/16 , H04M3/42221 , H04M3/4283 , H04M3/56 , H04M7/0057 , H04M7/1295 , H04M11/06 , H04M2203/2088 , H04M2203/5054 , H04N1/00957 , H04N1/031 , H04N1/0318 , H04N1/1934 , H04N1/1935 , H04N1/32106 , H04N1/40 , H04N5/04 , H04N5/073 , H04N5/126 , H04N5/2251 , H04N5/2257 , H04N5/23248 , H04N5/23254 , H04N5/23258 , H04N5/23267 , H04N5/2327 , H04N5/23277 , H04N5/272 , H04N5/38 , H04N5/4401 , H04N5/4448 , H04N5/445 , H04N5/45 , H04N5/46 , H04N5/64 , H04N5/642 , H04N5/66 , H04N5/76 , H04N5/775 , H04N5/85 , H04N5/907 , H04N7/0112 , H04N7/0122 , H04N7/163 , H04N7/17327 , H04N9/3129 , H04N9/641 , H04N9/642 , H04N9/7925 , H04N9/8042 , H04N19/109 , H04N19/115 , H04N19/139 , H04N19/152 , H04N19/174 , H04N19/19 , H04N19/194 , H04N19/51 , H04N19/517 , H04N19/527 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/91 , H04N21/234318 , H04N21/2368 , H04N21/2383 , H04N21/2543 , H04N21/2547 , H04N21/41415 , H04N21/4143 , H04N21/4181 , H04N21/42607 , H04N21/42653 , H04N21/4307 , H04N21/4312 , H04N21/4314 , H04N21/4318 , H04N21/433 , H04N21/4341 , H04N21/43622 , H04N21/43632 , H04N21/4382 , H04N21/44012 , H04N21/440218 , H04N21/4532 , H04N21/458 , H04N21/4621 , H04N21/4623 , H04N21/47211 , H04N21/6175 , H04N21/6187 , H04N21/6582 , H04N21/812 , H04N21/84 , H04N21/854 , H04N2201/0094 , H04N2201/02493 , H04N2201/03112 , H04N2201/03133 , H04N2201/03141 , H04N2201/03145 , H04N2201/03187 , H04N2201/3212 , H04N2201/3222 , H04N2201/3274 , H04Q3/0025 , H04Q3/60 , H04Q2213/1302 , H04Q2213/13039 , H04Q2213/1304 , H04Q2213/13076 , H04Q2213/13095 , H04Q2213/13109 , H04Q2213/13298 , H04Q2213/13349 , H04R1/028 , H04S7/301 , H04W4/06 , H04W4/10 , H04W4/12 , H04W4/14 , H04W8/245 , H04W8/26 , H04W8/265 , H04W12/10 , H04W24/00 , H04W28/00 , H04W28/18 , H04W28/24 , H04W28/26 , H04W36/02 , H04W40/00 , H04W40/02 , H04W48/08 , H04W52/0216 , H04W52/0225 , H04W52/0248 , H04W52/0274 , H04W52/30 , H04W56/00 , H04W64/00 , H04W68/00 , H04W72/042 , H04W72/1252 , H04W72/1268 , H04W74/008 , H04W74/0816 , H04W74/0833 , H04W76/10 , H04W76/12 , H04W76/18 , H04W76/30 , H04W76/34 , H04W76/45 , H04W80/00 , H04W84/042 , H04W84/08 , H04W84/12 , H04W88/06 , H04W88/08 , H04W88/085 , H04W88/16 , H04W92/02 , H04W92/12 , Y02D10/13 , Y02D70/168 , Y02D70/30 , Y02D70/40 , Y02D70/446 , Y02D70/449 , Y02D70/46 , Y10S370/906 , Y10S370/907 , Y10S707/99943
摘要： A method and circuitry for implementing digital multi-channel demodulation circuits. More particularly, embodiments of the present invention provide a digital multi-channel demodulator circuit. The demodulator includes a frequency-block down-converter that receives a multi-channel analog RF signal and shifts the multi-channel analog RF signal to a lower frequency band. An ADC receives the multi-channel analog RF signal from the frequency-block down-converter and converts the multi-channel analog RF signal to a multi-channel digital RF signal. A digital channel demultiplexer receives the multi-channel digital RF signal from the ADC and demultiplexes the multi-channel digital RF signal into separate digital RF channels.
摘要翻译：一种用于实现数字多通道解调电路的方法和电路。更具体地，本发明的实施例提供一种数字多通道解调器电路。解调器包括频率块下变频器，其接收多通道模拟RF信号并将多通道模拟RF信号移位到较低频带。 ADC从频块下变频器接收多通道模拟RF信号，并将多通道模拟RF信号转换为多通道数字RF信号。数字信道解复用器从ADC接收多信道数字RF信号，并将多信道数字RF信号解复用为分立的数字RF信道。

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