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1. 发明申请

US20130168841A1 Programmable Interposer with Conductive Particles 有权
标题翻译：可编程内插器与导电粒子
公开(公告)号：US20130168841A1
公开(公告)日：2013-07-04
申请号：US13340430
申请日：2011-12-29
申请人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K.V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
发明人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K.V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
IPC分类号： H01L23/495 , H01L21/326 , H05K1/11 , B82Y99/00
CPC分类号： H01L23/49827 , B82Y10/00 , H01L21/485 , H01L21/486 , H01L23/49822 , H01L2224/16225 , H05K1/029 , H05K3/4038 , H05K2201/0248 , H05K2201/026 , H05K2201/0323 , H05K2201/10378 , H05K2203/104 , H05K2203/105
摘要： An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.
摘要翻译：本公开的示例性实现包括具有顶部和底部接口电极和散布在可编程插值器内的导电粒子的可编程插值器。响应于将能量场施加到可编程内插器，导电颗粒能够在顶部和底部界面电极之间形成对准的构造，以便电连接顶部和底部界面电极。导电颗粒可具有导电外表面。此外，导电粒子可以是球形的。导电颗粒可以在可编程插入器中的界面层中的体积材料内，并且可以固化块状材料以确保顶部和底部界面电极之间的编程路径。

2. 发明申请

US20120295543A1 Method And System For Chip-To-Chip Mesh Networks 有权
标题翻译：芯片到网格网络的方法和系统
公开(公告)号：US20120295543A1
公开(公告)日：2012-11-22
申请号：US13564660
申请日：2012-08-01
申请人： Ahmadreza Rofougaran , Maryam Rofougaran
发明人： Ahmadreza Rofougaran , Maryam Rofougaran
IPC分类号： H04B5/00
CPC分类号： H04B1/40 , H01L23/66 , H01L25/0655 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
摘要： A wireless device comprising a plurality of chips may be operable to communicate wireless signals via a mesh network comprising a plurality of integrated directional antennas on the plurality of chips. Wireless signals may be communicated between the plurality of the chips and/or with devices external to the wireless device via the mesh network. Beam-formed wireless signals may be communicated via the plurality of integrated directional antennas. The plurality of chips may be integrated on a single package or on a plurality of packages, which may comprise one or more circuit boards. Wireless signals may be communicated with devices external to the single package via the mesh network. The directional antennas may comprise patch antennas and/or dipole antennas.
摘要翻译：包括多个芯片的无线设备可以用于经由包括多个芯片上的多个集成定向天线的网状网络来传送无线信号。无线信号可以经由网状网络在多个芯片之间和/或与无线设备外部的设备之间进行通信。波束形成的无线信号可以经由多个集成定向天线进行通信。多个芯片可以集成在单个封装上或多个封装上，其可以包括一个或多个电路板。无线信号可以经由网状网络与单个包装外部的装置通信。定向天线可以包括贴片天线和/或偶极天线。

3. 发明申请

US20110248356A1 Integrated one-time programmable semiconductor device pair 失效
标题翻译：集成一次可编程半导体器件对
公开(公告)号：US20110248356A1
公开(公告)日：2011-10-13
申请号：US12798766
申请日：2010-04-09
申请人： Douglas Smith
发明人： Douglas Smith
IPC分类号： H01L27/112 , H01L21/8246
CPC分类号： H01L27/112 , H01L27/11206
摘要： According to one disclosed embodiment, an integrated one-time programmable (OTP) semiconductor device pair includes a split-thickness dielectric under an electrode and over an isolation region formed in a doped semiconductor substrate, where a reduced-thickness center portion of the dielectric forms, in conjunction with the isolation region, programming regions of the OTP semiconductor device pair, and where the thicker, outer portions of the dielectric form dielectrics for transistor structures. In one embodiment, the split-thickness dielectric comprises a gate dielectric. In one embodiment, multiple OTP semiconductor device pairs are formed in an array that minimizes the number of connections required to program and sense states of specific OTP cells.
摘要翻译：根据一个所公开的实施例，集成一次可编程（OTP）半导体器件对包括在电极下面和形成在掺杂半导体衬底中的隔离区域上的分层厚度电介质，其中电介质的厚度减小的中心部分形成结合隔离区域，OTP半导体器件对的编程区域以及电介质的较厚的外部部分用于晶体管结构的电介质。在一个实施例中，分裂厚度电介质包括栅极电介质。在一个实施例中，以阵列形成多个OTP半导体器件对，其使得编程和感测特定OTP单元的状态所需的连接数量最小化。

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