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1. 发明专利

AU6643396A Multistate prom and decompressor 未知
公开(公告)号：AU6643396A
公开(公告)日：1997-02-26
申请号：AU6643396
申请日：1996-07-31
申请人： APLUS INTEGRATED CIRCUITS INC
发明人： LEE PETER W
IPC分类号： G11C11/56 , G11C27/00

2. 发明专利

AU2586395A Multistate rom memory cell array 未知
公开(公告)号：AU2586395A
公开(公告)日：1995-12-05
申请号：AU2586395
申请日：1995-05-12
申请人： APLUS INTEGRATED CIRCUITS INC
发明人： LEE PETER W
IPC分类号： G11C11/56 , G11C17/00

3. 发明专利

AU2825197A Flash memory address decoder with novel latch 未知
公开(公告)号：AU2825197A
公开(公告)日：1998-01-07
申请号：AU2825197
申请日：1997-05-05
申请人： APLUS INTEGRATED CIRCUITS INC
发明人： LEE PETER W , TSAO HSING-YA , HSU FU-CHANG
IPC分类号： G11C8/08 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115 , G11C11/34
摘要： A flash memory includes a flash transistor array, a wordline decoder, a bitline decoder, a sourceline decoder and a read/write controller. The read/write controller has a voltage terminal to receive an input voltage and a data terminal to receive a new data signal. A sense amplifier is coupled to the bitline decoder and configured to sense a signal on a selected bitline and to generate an internal old data signal. A data comparator is coupled to the data terminal and the sense amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to read a selected cell in the flash transistor array, a program set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts. The voltage generator is coupled to the step counter and configured to generate a wordline high voltage (WLHV) signal based on the step count. The WLHV signal is delivered to a selected multistate cell by the wordline decoder to read the contents of the selected multistate cell. Each step compares the old data and the new data in order to determine which memory cells to change. Advantages of the invention include increased flexibility of programming and erasing and improved memory longevity.

4. 发明专利

AU2596597A Flash memory address decoder with novel latch structure 未知
公开(公告)号：AU2596597A
公开(公告)日：1997-10-22
申请号：AU2596597
申请日：1997-03-28
申请人： APLUS INTEGRATED CIRCUITS INC
发明人： LEE PETER W , TSAO HSING-YA , HSU FU-CHANG
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06

5. 发明专利

AU2604295A Flat-cell rom and decoder 未知
公开(公告)号：AU2604295A
公开(公告)日：1995-12-21
申请号：AU2604295
申请日：1995-05-24
申请人： APLUS INTEGRATED CIRCUITS INC
发明人： LEE PETER W
IPC分类号： H01L27/112 , G11C17/12 , H01L21/8246 , G11C17/00
摘要： A flat-cell ROM array includes a bank of field effect transistors, each having a source, drain and gate, formed by ion implantation between columns of buried N+ and under rows of polysilicon, wherein adjacent columns of buried N+ are the source and drain of at least one transistor and a corresponding row of polysilicon is the gate of the transistor. Each of these transistors is programmed to have one of a plurality of threshold voltages depending on a desired storage value. Attached to the bank of transistors is an upper selector network associated with the bank connected to a first class of alternating sets of the columns, and a lower selector network associated with the bank connected to a second class of alternating sets of the columns. A method provides steps for performing the present invention.

6. 发明申请

WO1997049086A1 FLASH MEMORY ADDRESS DECODER WITH NOVEL LATCH 审中-公开
标题翻译：闪存存储器地址解码器与新的锁定
公开(公告)号：WO1997049086A1
公开(公告)日：1997-12-24
申请号：PCT/US1997007456
申请日：1997-05-05
申请人： APLUS INTEGRATED CIRCUITS, INC.
发明人： APLUS INTEGRATED CIRCUITS, INC. , LEE, Peter, W. , TSAO, Hsing-Ya , HSU, Fu-Chang
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/08 , G11C8/14 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/3413 , G11C16/3431 , G11C2211/5644 , H01L27/115
摘要： A flash memory (10) includes a flash transistor array (12a, 12b, 12i), a wordline decoder (14), a bitline decoder (18), a sourceline decoder (22) and a read/write controller (26). The read/write controller (26) has a voltage terminal to receive an input voltage and a data terminal configured to sense a signal on a selected bitline and to generate an internal old amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts. The voltage generator is coupled to the step counter and configured to generate a wordline high voltage (WLHV) signal based on the step count. The WLHV signal is delivered to a selected multistate cell by the wordline decoder to read the contents of the selected multistate cell. Each step compares the old data and the new data in order to determine which memory cells to change. Advantages of the invention include increased flexibility of programming and erasing and improved memory longevity.
摘要翻译：闪速存储器（10）包括闪存晶体管阵列（12a，12b，12i），字线解码器（14），位线解码器（18），源线解码器（22）和读/写控制器（26）。读/写控制器（26）具有用于接收输入电压的电压端子和被配置为感测选定位线上的信号并产生内部旧放大器并被配置为将新数据信号与旧数据信号进行比较的数据端并产生比较器信号。电压发生器被配置为选择性地施加读取的一组电压以编程所选择的单元和擦除电压组以擦除所选择的单元。在多状态实施例中，读/写控制器还包括配置成产生多个步数的步数计数器。电压发生器耦合到步进计数器并且被配置为基于步数产生字线高电压（WLHV）信号。 WLHV信号由字线解码器传送到选定的多状态单元，以读取所选择的多态单元的内容。每个步骤都比较旧数据和新数据，以确定要更改的存储单元。本发明的优点包括增加编程和擦除的灵活性并改善记忆寿命。

7. 发明申请

WO1997037356A1 FLASH MEMORY ADDRESS DECODER WITH NOVEL LATCH STRUCTURE 审中-公开
标题翻译：具有新型锁定结构的闪存存储器地址解码器
公开(公告)号：WO1997037356A1
公开(公告)日：1997-10-09
申请号：PCT/US1997005159
申请日：1997-03-28
申请人： APLUS INTEGRATED CIRCUITS, INC. , LEE, Peter, W. , TSAO, Hsing-Ya , HSU, Fu-Chang
发明人： APLUS INTEGRATED CIRCUITS, INC.
IPC分类号： G11C16/06
CPC分类号： G11C16/3413 , G11C7/18 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/3404 , G11C16/3409 , G11C2211/5642 , G11C2216/20 , H01L27/115
摘要： A flash memory address decoder with a novel latch structure includes an address terminal to receive an address signal, a procedure terminal to receive a procedure signal, a power terminal to receive a power signal and a flash transistor array having a plurality of wordlines, sourcelines and bitlines. A sourceline decoder is coupled to the address terminal and the power terminals and configured to decode a portion of the address and provide an operational voltage on at least one of the sourcelines. A wordline decoder is coupled to the address terminal and the power terminal and includes a plurality of latches coupled to the wordlines. The wordline decoder is configured to decode a portion of the address and to latch selected wordlines to simultaneously provide a plurality of operational voltages on different ones of the wordlines. A bitline decoder is coupled to the address terminal and configured to decode a portion of the address and to select a plurality of the bitlines as selected bitlines. A sense amplifier is coupled to the bitline decoder and configured to sense current on the selected bitlines and to generate a data word corresponding to the current. A memory controller is coupled to the procedure terminal, the power terminal, the sourceline decoder, the wordline decoder, the bitline decoder and the sense amplifier, and is configured to control the sourceline decoder, the wordline decoder, the bitline decoder and the sense amplifier to perform a procedure responsive to the procedure signal.
摘要翻译：具有新颖锁存结构的闪存地址解码器包括接收地址信号的地址端子，接收过程信号的过程终端，接收电源信号的电源端子和具有多个字线的闪存晶体管阵列，源极线和位线。源线解码器耦合到地址终端和电源终端，并且被配置为解码地址的一部分并在至少一个源线上提供工作电压。字线解码器耦合到地址端子和电源端子，并且包括耦合到字线的多个锁存器。字线解码器被配置为对地址的一部分进行解码，并锁存所选择的字线，以在不同的字线上同时提供多个操作电压。位线解码器耦合到地址终端，并且被配置为对地址的一部分进行解码，并选择多个位线作为选择的位线。读出放大器耦合到位线解码器，并且被配置为感测所选位线上的电流并产生对应于电流的数据字。存储器控制器耦合到过程终端，电源终端，源线解码器，字线解码器，位线解码器和读出放大器，并且被配置为控制源线解码器，字线解码器，位线解码器和读出放大器以执行响应于过程信号的过程。

8. 发明申请

WO1995033266A1 FLAT-CELL ROM AND DECODER 审中-公开
标题翻译：平板ROM和解码器
公开(公告)号：WO1995033266A1
公开(公告)日：1995-12-07
申请号：PCT/US1995006624
申请日：1995-05-24
申请人： APLUS INTEGRATED CIRCUITS, INC.
发明人： APLUS INTEGRATED CIRCUITS, INC. , LEE, Peter, W.
IPC分类号： G11C17/00
CPC分类号： G11C17/126
摘要： A flat-cell ROM array (10) comprises a bank of field effect transistors, each having a source, drain and gate, formed by ion implantation between columns (54a-i) of buried N+ and under rows of polysilicon (56), wherein adjacent columns of buried N+ are the source and drain of at least one transistor and a corresponding row of polysilicon is the gate of the transistor. Each of these transistors is programmed to have one of a plurality of threshold voltages depending on a desired storage value. Attached to the bank of transistors is an upper selector network (14) associated with the bank connected to a first class of alternating sets of the columns, and a lower selector network (16) associated with the bank connected to a second class of alternating sets of the columns. A method provides steps for performing the present invention.
摘要翻译：平板单元ROM阵列（10）包括一组场效应晶体管，每一个具有源极，漏极和栅极，通过在掩埋N +的列（54a-i）和多晶硅行（56）之间的离子注入形成，其中埋入N +的相邻列是至少一个晶体管的源极和漏极，并且相应的多晶硅行是晶体管的栅极。根据期望的存储值，将这些晶体管中的每一个编程为具有多个阈值电压中的一个。连接到晶体管组的是与连接到第一类交替的列的组相关联的上选择器网络（14），以及与连接到第二类交替集合的组相关联的下选择器网络（16）的列。一种方法提供了执行本发明的步骤。

9. 发明申请

WO1998015959A1 FLASH MEMORY WITH DIVIDED BITLINE 审中-公开
标题翻译：带有分数字的闪存
公开(公告)号：WO1998015959A1
公开(公告)日：1998-04-16
申请号：PCT/US1997018042
申请日：1997-10-03
申请人： APLUS INTEGRATED CIRCUITS, INC.
发明人： APLUS INTEGRATED CIRCUITS, INC. , LEE, Peter, W. , TSAO, Hsing-Ha , HSU, Fu-Chang
IPC分类号： G11C16/00
CPC分类号： G11C16/3409 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/08 , G11C8/10 , G11C8/14 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/34 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , H01L27/115
摘要： A flash memory includes a bank of flash transistors forming a plurality of rows and a plurality of columns, each flash transistor having a gate, drain and source, where the gates of flash transistors in each row are coupled to common wordlines (16a0-16a3), the drains of flash transistors in each column are coupled to common metal 1 lines (18a0-18a7) divided into even metal 1 lines and odd metal 1 lines and the sources of flash transistors are coupled to a common sourceline (20a). A set of first selection transistors (24a0-24a3) are coupled between even metal 1 lines and metal 2 lines (24a0-24a3) having a pitch twice that of the metal 1 lines and controlled by a first select signal (26a) to selectively couple the even metal 1 lines to the metal 2 lines. A set of second selection transistos (28a0-28a3) are coupled between the odd metal 1 lines and the metal 2 lines and controlled by a second select signal (26b) to selectively couple the odd metal 1 lines to the metal 2 lines. In one embodiment, the set of first selection transistors are large in comparison to the flash transistors. Advantages of the invention include improved selection of memory cells, higher memory cell density and lower resistance in the memory cell selection circuitry.
摘要翻译：闪速存储器包括形成多行和多列的闪存晶体管组，每个闪存晶体管具有栅极，漏极和源极，其中每行中的闪存晶体管的栅极耦合到公共字线（16a0-16a3）每列中的闪存晶体管的漏极耦合到分为偶数金属1线和奇数金属1线的公共金属1线（18a0-18a7），并且闪存晶体管的源极耦合到公共源极线（20a）。一组第一选择晶体管（24a0-24a3）耦合在偶数金属1线和金属2线（24a0-24a3）之间，金属线（24a0-24a3）的间距是金属1线的两倍，并由第一选择信号（26a）控制，以选择性地耦合均匀金属1线到金属2线。一组第二选择截止（28a0-28a3）耦合在奇数金属1线和金属2线之间，并由第二选择信号（26b）控制，以将奇数金属1线选择性地耦合到金属2线。在一个实施例中，与闪存晶体管相比，该组第一选择晶体管较大。本发明的优点包括存储器单元的改进选择，更高的存储单元密度和较低的存储单元选择电路中的电阻。

10. 发明申请

WO1998020401A1 POSITIVE/NEGATIVE HIGH VOLTAGE CHARGE PUMP SYSTEM 审中-公开
标题翻译：积极/负极高压充电泵系统
公开(公告)号：WO1998020401A1
公开(公告)日：1998-05-14
申请号：PCT/US1997020046
申请日：1997-11-03
申请人： APLUS INTEGRATED CIRCUITS, INC.
发明人： APLUS INTEGRATED CIRCUITS, INC. , LEE, Peter, W. , TSAO, Hsing-Ya , HSU, Fu-Chang
IPC分类号： G05F03/02
CPC分类号： G05F3/20 , G11C5/145 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/14 , G11C16/16 , G11C16/30 , H02M3/073
摘要： An electronically reconfigurable two-phase high voltage generator circuit (230) which outputs positive (Vpp) or negative (Vpn) voltage, depending upon the desired operation. The circuit includes a plurality of series-connected charge multiplier stages (D and C) that each comprise a diode (D) and a charging capacitor (C). Collectively, the stages define an anode node and a cathode node. The output voltage being provided to a load capacitor (CLOAD). A respective one of two non-overlapping phase signals ( phi 1 and phi 2) is coupled to each charging capacitor such that adjacent charging capacitors are driven by different phases. First and second two-way multiplexers (MUX1 and MUX2) control voltage levels at the anode and cathode nodes, to determine positive or negative mode circuit operation. The diodes may be PMOS or NMOS transistors, and preferably Vt-cancellation is provided for each charging stage. Further, the circuit includes substrate-well protection.
摘要翻译：根据期望的操作，电子可重新配置的两相高压发生器电路（230），其输出正（Vpp）或负（Vpn）电压。该电路包括多个串联连接的电荷倍增器级（D和C），每个均包括一个二极管（D）和一个充电电容器（C）。这些阶段总体上定义了阳极节点和阴极节点。输出电压被提供给负载电容器（CLOAD）。两个非重叠相位信号（phi 1和phi 2）中的相应一个耦合到每个充电电容器，使得相邻的充电电容器由不同的相位驱动。第一和第二双向多路复用器（MUX1和MUX2）控制阳极和阴极节点处的电压电平，以确定正或负模式电路操作。二极管可以是PMOS或NMOS晶体管，并且优选地为每个充电阶段提供Vt取消。此外，电路包括衬底井保护。

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