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1. 发明申请

WO2006023008A2 AN INTERCONNECTION FABRIC USING SWITCHING NETWORKS IN HIERARCHY 审中-公开
标题翻译：使用切换网络的互连织物
公开(公告)号：WO2006023008A2
公开(公告)日：2006-03-02
申请号：PCT/US2005/020945
申请日：2005-06-15
申请人： ADVANTAGE LOGIC, INC. , PANI, Peter, M. , TING, Benjamin, S.
发明人： PANI, Peter, M. , TING, Benjamin, S.
IPC分类号： H04L12/50
CPC分类号： H04L49/15
摘要： An interconnection fabric using switching networks hierarchically to allow interconnections of large number of a first plurality of conductors to a large number of k plurality of conductors is described. The resulting interconnection fabric can be used in switching networks, routers and programmable logic circuits.
摘要翻译：描述了分层使用交换网络以允许大量第一多个导体与多个k个多个导体的互连的互连结构。所产生的互连结构可用于交换网络，路由器和可编程逻辑电路。

2. 发明申请

WO1995020197A1 APPARATUS AND METHOD FOR PARTITIONING RESOURCES FOR INTERCONNECTIONS 审中-公开
标题翻译：用于互连的资源分配的装置和方法
公开(公告)号：WO1995020197A1
公开(公告)日：1995-07-27
申请号：PCT/US1995000313
申请日：1995-01-10
申请人： ADVANTAGE LOGIC, INC.
发明人： ADVANTAGE LOGIC, INC. , TING, Benjamin, S.
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus and method for determining how to interconnect a plurality of components of a system, given a limited number of interconnect resources available to a device. First, it is determined whether the system meets the capacity constraints of the device. If the requirements exceed the capacity, a larger device is necessary. Otherwise, a topmost interconnection level is established. This topmost level is partitioned into four different partitions. The components are assigned and optimized to these four partitions. Next, a lower level of interconnection is established for one or more of these four partitions. Each of these lower levels are, in turn, partitioned into four different partitions. Components are then assigned and optimized to these partitions. This process is repeated for even lower levels until routing of the interconnections for the system is achieved. Thereupon, the components are physically interconnected from the lower levels to the topmost level according to the routing pattern that was determined in the establishing, partitioning, and said optimizing steps.
摘要翻译：给定有限数量的可用于设备的互连资源的用于确定如何互连系统的多个组件的装置和方法。首先，确定系统是否满足设备的容量限制。如果要求超过容量，则需要更大的设备。否则，建立最高的互连级别。这个最上层分为四个不同的分区。为这四个分区分配和优化组件。接下来，为这四个分区中的一个或多个建立较低级别的互连。这些较低级别中的每一个又分成四个不同的分区。然后将组件分配并优化到这些分区。对于甚至更低的级别重复该过程，直到实现用于系统的互连的路由。因此，根据在建立，分区和所述优化步骤中确定的路由模式，组件从较低级别物理地互连到最高级别。

3. 发明申请

WO2005104375A1 A SCALABLE NON-BLOCKING SWITCHING NETWORK FOR PROGRAMMABLE LOGIC 审中-公开
标题翻译：用于可编程逻辑的可扩展非阻塞切换网络
公开(公告)号：WO2005104375A1
公开(公告)日：2005-11-03
申请号：PCT/US2005/006583
申请日：2005-02-28
申请人： ADVANTAGE LOGIC, INC. , PANI, Peter, M. , TING, Benjamin, S.
发明人： PANI, Peter, M. , TING, Benjamin, S.
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K17/002 , H04L49/15 , H04L49/1515 , Y10T29/49002 , Y10T29/49117
摘要： A scalable non-blocking switching network (SN) having switches (151-160) and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN (200) can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors (101-104), through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
摘要翻译：具有开关（151-160）和中间（阶段）导体的可扩展非阻塞交换网络（SN），其用于在相应的互连资源约束条件下以大致无限制的方式将第一多个导体连接到其它多组导体。 SN（200）可以应用在广泛的应用中，一起或分层，以提供在网络，路由器和可编程逻辑电路中使用的大型交换机网络。 SN用于通过SN将第一组导体（101-104）连接到给定逻辑电路层级中的多组导体，由此多组中的每一组中的导体是等效的或可交换的，通过构造，使第一组导体在用于下一级电路层级时相当。 SN可针对大型导体组进行扩展，可以分级使用，以实现大尺寸电路之间的可编程互连。

4. 发明申请

WO1995004404A1 ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS 审中-公开
标题翻译：可编程逻辑电路的架构和互连方案
公开(公告)号：WO1995004404A1
公开(公告)日：1995-02-09
申请号：PCT/US1994007187
申请日：1994-06-24
申请人： ADVANTAGE LOGIC, INC.
发明人： ADVANTAGE LOGIC, INC. , TING, Benjamin, S.
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. A uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. A uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.
摘要翻译：用于现场可编程门阵列（FPGA）的架构和分布式分层互连方案。 FPGA由多个对输入信号执行逻辑功能的单元组成。可编程的内连接将属于逻辑集群的小区的每个输出之间的连接性提供给属于该逻辑集群的每个其他小区的至少一个输入。一组可编程块连接器用于提供单元的逻辑簇之间的可连接性以及对分层路由网络的可访问性。均匀分布的第一层路由网络线路用于提供块连接器组之间的连接。实现均匀分布的第二层路由网络线路，以提供不同第一层路由网络线路之间的连接性。交换网络用于提供块连接器与对应于第一层的路由网络线路之间的可连接性。其他交换网络提供对应于第一层的路由网络线路与对应于第二层的路由网络线路之间的可连接性。实现了额外的均匀分布的路由网络线路层以提供不同的现有路由网络线路之间的可连接性。当单元的数量作为阵列中的两个先前单元计数的平方函数增加时，添加另外的路由层，而路由线的长度和路由线的数量增加为两个的线性函数。可编程双向passgates用作开关，用于控制要连接的路由网络线路。

5. 发明专利

AT255766T 未知
公开(公告)号：AT255766T
公开(公告)日：2003-12-15
申请号：AT96921471
申请日：1996-06-14
申请人： ADVANTAGE LOGIC INC
发明人： PANI PETER M , TING BENJAMIN S , MA BENNY
IPC分类号： G11C16/04 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H03K17/687 , H03K17/693
摘要： A bidirectional passgate switch for connecting two conductors utilizes technology such as electrically erasable programmable read only memory (EEPROM). The switch includes two EEPROM components wherein the floating gates of the components are shared. In one embodiment a first n-channel passgate transistor is used for programming and storage of the state of the switch. The oxide of the first transistor is a thin oxide to enable ease of programming. A second n-channel passgate transistor functions as the bidirectional switch wherein the source and drain terminals are coupled to the routing lines to be selectively connected. The second transistor oxide is a thick oxide to minimize the leakage due to tunneling. Thus, the programming lines and routing lines are separated, making the programming process simpler while minimizing leakage.

6. 发明申请

WO2010065183A1 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS 审中-公开
标题翻译：具有增强的互连信号的可互换切换网络
公开(公告)号：WO2010065183A1
公开(公告)日：2010-06-10
申请号：PCT/US2009/058818
申请日：2009-09-29
申请人： ADVANTAGE LOGIC, INC. , PANI, Peter, M. , TING, Benjamin, S.
发明人： PANI, Peter, M. , TING, Benjamin, S.
IPC分类号： H04L12/28
CPC分类号： H03K19/17736 , H01L21/768 , Y10T29/4913
摘要： In one embodiment, the integrated circuit has a L- level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
摘要翻译：在一个实施例中，集成电路具有包括L级中间导体的L电平可置换开关网络（L-PSN）。集成电路可用于电子设备，如交换网络，路由器和可编程逻辑电路等。

7. 发明申请

WO2006023008A3 AN INTERCONNECTION FABRIC USING SWITCHING NETWORKS IN HIERARCHY 审中-公开
标题翻译：使用切换网络的互连织物
公开(公告)号：WO2006023008A3
公开(公告)日：2007-01-25
申请号：PCT/US2005020945
申请日：2005-06-15
申请人： ADVANTAGE LOGIC INC , PANI PETER M , TING BENJAMIN S
发明人： PANI PETER M , TING BENJAMIN S
IPC分类号： H04Q11/00 , H03K19/00 , H03K19/173
CPC分类号： H04L49/15
摘要： An interconnection fabric using switching networks hierarchically to allow interconnections of large number of a first plurality of conductors to a large number of k plurality of conductors is described. The resulting interconnection fabric can be used in switching networks, routers and programmable logic circuits.
摘要翻译：描述了分层使用交换网络以允许大量第一多个导体与多个k个多个导体的互连的互连结构。所产生的互连结构可用于交换网络，路由器和可编程逻辑电路。

8. 发明专利

DE69630958D1 未知
公开(公告)号：DE69630958D1
公开(公告)日：2004-01-15
申请号：DE69630958
申请日：1996-06-14
申请人： ADVANTAGE LOGIC INC
发明人： PANI M , TING S , MA BENNY
IPC分类号： G11C16/04 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H03K17/687 , H03K17/693
摘要： A bidirectional passgate switch for connecting two conductors utilizes technology such as electrically erasable programmable read only memory (EEPROM). The switch includes two EEPROM components wherein the floating gates of the components are shared. In one embodiment a first n-channel passgate transistor is used for programming and storage of the state of the switch. The oxide of the first transistor is a thin oxide to enable ease of programming. A second n-channel passgate transistor functions as the bidirectional switch wherein the source and drain terminals are coupled to the routing lines to be selectively connected. The second transistor oxide is a thick oxide to minimize the leakage due to tunneling. Thus, the programming lines and routing lines are separated, making the programming process simpler while minimizing leakage.

9. 发明专利

AU1562195A Apparatus and method for partitioning resources for interconnections 未知
公开(公告)号：AU1562195A
公开(公告)日：1995-08-08
申请号：AU1562195
申请日：1995-01-10
申请人： ADVANTAGE LOGIC INC
发明人： TING BENJAMIN S
IPC分类号： G06F17/50
摘要： An apparatus and method for determining how to interconnect a plurality of components of a system, given a limited number of interconnect resources available to a device. First, it is determined whether the system meets the capacity constraints of the device. If the requirements exceed the capacity, a larger device is necessary. Otherwise, a topmost interconnection level is established. This topmost level is partitioned into four different partitions. The components are assigned and optimized to these four partitions. Next, a lower level of interconnection is established for one or more of these four partitions. Each of these lower levels are, in turn, partitioned into four different partitions. Components are then assigned and optimized to these partitions. This process is repeated for even lower levels until routing of the interconnections for the system is achieved. Thereupon, the components are physically interconnected from the lower levels to the topmost level according to the routing pattern that was determined in the establishing, partitioning, and said optimizing steps.

10. 发明专利

AU7356294A Architecture and interconnect scheme for programmable logic circuits 未知
公开(公告)号：AU7356294A
公开(公告)日：1995-02-28
申请号：AU7356294
申请日：1994-06-24
申请人： ADVANTAGE LOGIC INC
发明人： TING BENJAMIN S
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
摘要： A programmable logic circuit comprising: an input/output interface (102) for inputting signals to the programmable logic circuit; a plurality of cells coupled to the input/output interface, each of said cells capable of performing digital processing on signals; a first set of routing lines for coupling a plurality of cells to form logical clusters (107) of cells, said first set of routing lines further providing programmable couplings to cells or other logical clusters; a second set of routing lines (108) for coupling a plurality of logical clusters to form a logical block of logical clusters of cells, wherein each cell is programmably coupled to the second set of routing lines; and a plurality of sets of higher level global routing lines, each set of global routing lines spanning a plurality of logical blocks, wherein each set of higher level global routing lines can be programmably coupled to the second set of routing lines, said first set of routing lines and cells through the second set of routing lines.

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