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81. 发明授权

US07626451B2 Data demodulation using an asynchronous clock 有权
标题翻译：使用异步时钟进行数据解调
公开(公告)号：US07626451B2
公开(公告)日：2009-12-01
申请号：US10649218
申请日：2003-08-26
申请人： Larry Kirn
发明人： Larry Kirn
IPC分类号： H03K9/08 , H03M5/08
CPC分类号： H04L25/4902
摘要： A method and accompanying circuitry for asynchronous data demodulation uses sorted pulsewidth measurement based on an asynchronous clock. Lock-on of the data stream by such a system is accomplished by measured pulsewidth, rather than inferred frequency. The method broadly comprises the steps of measuring a temporal aspect of the asynchronous clock, and locking onto the data stream in accordance with the measured periods. In the preferred embodiment, the temporal aspect is a ratio of measured periods. Conveniently, a ratio of 2:1 may be used.
摘要翻译：用于异步数据解调的方法和相关电路使用基于异步时钟的排序脉宽测量。通过这种系统锁定数据流是通过测量的脉冲宽度来实现的，而不是推断出的频率。该方法广泛地包括以下步骤：测量异步时钟的时间方面，并根据测量的周期锁定到数据流上。在优选实施例中，时间方面是测量周期的比率。方便地，可以使用2:1的比例。

82. 发明授权

US07515072B2 Method and apparatus for converting PCM to PWM 有权
标题翻译：将PCM转换为PWM的方法和装置
公开(公告)号：US07515072B2
公开(公告)日：2009-04-07
申请号：US10945625
申请日：2004-09-21
申请人： Ana Borisavljevic
发明人： Ana Borisavljevic
IPC分类号： H03M5/08
CPC分类号： H03M3/506 , H03M5/08 , H03M7/3022
摘要： A circuit for converting from an input serial pulse code modulated (PCM) digital signal to an output pulse width modulated (PWM) digital signal for driving a switching audio amplifier requiring a pulse width modulated input signal, the circuit comprising a sample rate converter receiving the input serial PCM digital signal at a first sampling frequency and converting the input serial PCM digital signal to a second serial PCM digital signal at a second frequency if the first sampling frequency is lower than the second frequency, a digital filter stage for up-sampling the second serial PCM digital signal to a third frequency and converting the second serial PCM digital signal to a parallel digital signal, a volume control stage receiving the parallel digital signal and generating a volume adjusted parallel digital signal in accordance with a digital volume command control signal, a digital cross-point estimator stage for calculating a cross-point between the volume adjusted parallel digital signal and a digital ramp signal and generating a parallel digital signal representing a desired pulse width modulation of the switching audio amplifier, a quantizing stage for quantizing the parallel digital signal representing the desired pulse width modulation into a quantized parallel digital signal representing the pulse width modulation to be applied to the switching audio amplifier; and a PWM generation stage for converting the quantized parallel digital signal into a PWM signal for driving the switching audio amplifier.
摘要翻译：一种用于从输入串行脉冲编码调制（PCM）数字信号转换为输出脉宽调制（PWM）数字信号的电路，用于驱动需要脉宽调制输入信号的开关音频放大器，该电路包括一个采样率转换器，以第一采样频率输入串行PCM数字信号，并且如果第一采样频率低于第二频率，则将输入串行PCM数字信号转换成第二串行PCM数字信号，第二采样频率低于第二频率;数字滤波器级将第二串行PCM数字信号转换为第三频率并将第二串行PCM数字信号转换为并行数字信号，音量控制级接收并行数字信号并根据数字音量指令控制信号产生音量调节的并行数字信号，一个数字交叉点估计器阶段，用于计算体积调整的并行数字之间的交叉点数字斜坡信号和数字斜坡信号，并产生表示开关音频放大器的期望脉冲宽度调制的并行数字信号;量化级，用于将表示所需脉冲宽度调制的并行数字信号量化为表示脉冲宽度的量化并行数字信号调制应用于开关音频放大器; 以及用于将量化的并行数字信号转换为用于驱动开关音频放大器的PWM信号的PWM生成级。

83. 发明申请

US20080297382A1 PULSE-WIDTH MODULATION OF PULSE-CODE MODULATED SIGNALS AT SELECTABLE OR DYNAMICALLY VARYING SAMPLE RATES 有权
标题翻译：脉冲代码调制信号在可选或动态变化率下的脉冲宽度调制
公开(公告)号：US20080297382A1
公开(公告)日：2008-12-04
申请号：US12127173
申请日：2008-05-27
申请人： Lars Risbo
发明人： Lars Risbo
IPC分类号： H03M5/08
CPC分类号： H03M5/08 , G10L19/10
摘要： Digital audio circuitry including modulation circuitry (35; 135) for generating a pulse-width modulated (PWM) signal from processed pulse-code modulated (PCM) audio signals. The modulation circuitry includes a duration quantizer function (32) that generates a sequence of duration values d(k) from received PCM samples, quantized to integer multiples of periods of a master PWM clock (CLKpwm). The duration quantizer function also produces a feedback PCM value x(k) from each quantized duration value d(k) that is applied to a loop filter (36), the output of which modifies the received PCM sample stream to suppress quantization noise. Transient effects caused by modulation or abrupt changes in the desired PWM period are suppressed by digitally filtering (34; 134) the PWM period sample stream.
摘要翻译：数字音频电路包括用于从经处理的脉码调制（PCM）音频信号产生脉冲宽度调制（PWM）信号的调制电路（35; 135）。调制电路包括持续时间量化器功能（32），其从接收的PCM采样生成持续时间值d（k）的序列，量化到主PWM时钟（CLKpwm）的周期的整数倍。持续时间量化器功能还从施加到环路滤波器（36）的每个量化持续时间值d（k）产生反馈PCM值x（k），其输出修改接收的PCM采样流以抑制量化噪声。通过PWM周期采样流的数字滤波（34; 134）来抑制由期望的PWM周期中的调制或突然变化引起的瞬态效应。

84. 发明授权

US07391346B1 Switching amplifier system and method 有权
标题翻译：开关放大器系统及方法
公开(公告)号：US07391346B1
公开(公告)日：2008-06-24
申请号：US11702269
申请日：2007-02-05
申请人： Michael Determan , Kamlesh Khilnani
发明人： Michael Determan , Kamlesh Khilnani
IPC分类号： H03M5/08 , H03M1/82 , H03K9/08
CPC分类号： H03M5/08 , H03F3/217 , H03F2200/03 , H03F2200/321 , H03F2200/351 , H03M3/506 , H03M7/3026 , H03M7/3042
摘要： A switching amplifier system and method is disclosed. In a particular embodiment, a pulse width modulation frame size is determined based on a sample rate of a digital input signal. Data associated with the first digital input signal is modified based on the pulse width modulation frame size. A pulse width modulation signal is generated in response to the modified data.
摘要翻译：公开了一种开关放大器系统和方法。在特定实施例中，基于数字输入信号的采样率来确定脉宽调制帧大小。与第一数字输入信号相关联的数据基于脉宽调制帧大小被修改。响应于修改的数据产生脉宽调制信号。

85. 发明申请

US20080111720A1 Cycle time to digital converter 失效
标题翻译：循环时间到数字转换器
公开(公告)号：US20080111720A1
公开(公告)日：2008-05-15
申请号：US11826339
申请日：2007-07-13
申请人： Hong-Yi Huang , Sheng-Dar Wu , Yuan-Hua Chu
发明人： Hong-Yi Huang , Sheng-Dar Wu , Yuan-Hua Chu
IPC分类号： H03M5/08
CPC分类号： G04F10/005
摘要： A cycle time to digital converter comprises a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.
摘要翻译：数字转换器的周期时间包括双延迟锁定环路，多相采样检测器和VDL采样检测器。双延迟锁定环路产生对应于第一延迟时间的第一电压和对应于第二延迟时间的第二电压。多相采样检测器接收第一起始信号，第一停止信号和第一电压以检测粗延迟时间，根据粗延迟时间产生第一组信号，将第一停止信号延迟公共延迟时间以产生第二停止并且将第一起始信号延迟粗延迟时间和公共延迟时间以产生第二起始信号。 VDL采样检测器接收第一电压，第二电压，第二起始信号和第二停止信号，用于检测精细的延迟时间，并根据微小的延迟时间产生第二组信号。

86. 发明授权

US06979987B2 METHOD OF REGULATING AN OUTPUT VOLTAGE OF A POWER CONVERTER BY SENSING THE OUTPUT VOLTAGE DURING A FIRST TIME INTERVAL AND CALCULATING A NEXT CURRENT VALUE IN AN INDUCTOR SUFFICIENT TO BRING THE OUTPUT VOLTAGE TO A TARGET VOLTAGE WITHIN A SECOND TIME INTERVAL IMMEDIATELY FOLLOWING THE FIRST TIME INTERVAL AND VARYING A DUTY CYCLE OF A SWITCH DURING THE SECOND TIME INTERVAL 有权
标题翻译：通过在第一时间间隔期间感测输出电压来调节功率转换器的输出电压的方法，并计算在电感器中的下一个电流值，以便在第一时间间隔之后的第二时间间隔内将输出电压输出到目标电压并在第二时间间隔内改变开关的占空比
公开(公告)号：US06979987B2
公开(公告)日：2005-12-27
申请号：US10295580
申请日：2002-11-14
申请人： Kent Kernahan , David F. Fraser , Jack Roan
发明人： Kent Kernahan , David F. Fraser , Jack Roan
IPC分类号： G05F3/26 , H02J7/00 , H02M1/084 , H02M3/156 , H02M3/157 , H02M3/158 , H03M5/08 , G05F1/40 , H02M7/00
CPC分类号： H02M3/157 , G05F3/262 , H02J7/0065 , H02M1/0845 , H02M3/156 , H02M3/1588 , H02M2001/0012 , H02M2001/007 , H02M2001/008 , H03M5/08 , H05B41/2828 , Y02B20/186 , Y02B70/1466 , Y10T307/438 , Y10T307/469
摘要： The output voltage of a power converter is controlled by comparing the output voltage to a target output voltage during a first time interval and calculating an inductor current required in a second time interval immediately following the first time interval to increase the output voltage to the target output voltage. A duty cycle of a switch is varied to modify the current in the inductor during the second time interval according to the calculated inductor current. In one embodiment a fixed duty cycle response is provided if the output voltage is less than a predefined maximum and greater than a predefined minimum. In another embodiment the duty cycle of the switch is bounded by a predetermined maximum and minimum value.
摘要翻译：功率转换器的输出电压通过在第一时间间隔期间比较输出电压与目标输出电压并计算在第一时间间隔之后的第二时间间隔中所需的电感器电流来控制，以将输出电压增加到目标输出电压。改变开关的占空比根据所计算的电感器电流在第二时间间隔期间改变电感器中的电流。在一个实施例中，如果输出电压小于预定最大值并且大于预定最小值，则提供固定占空比响应。在另一个实施例中，开关的占空比由预定的最大值和最小值限制。

87. 发明申请

US20050078021A1 Dual phase pulse modulation encoder circuit 有权
标题翻译：双相脉冲调制编码电路
公开(公告)号：US20050078021A1
公开(公告)日：2005-04-14
申请号：US10836703
申请日：2004-04-29
申请人： Daniel Cohen , John Fagan , Mark Bossard
发明人： Daniel Cohen , John Fagan , Mark Bossard
IPC分类号： H03M20060101 , H03M5/06 , H03M5/08 , H04L27/04 , H04L27/12 , H04L27/20
CPC分类号： H03M5/08
摘要： An dual phase pulse modulation (DPPM) encoder circuit converts data into a series of high and low signal pulses, each of whose time durations or pulse widths represents a group of M data bits, with the alternating high and low pulses representing successive groups. The encoder circuit may include a set of parallel-in, serial-out shift registers that subdivide received data words into the M-bit groups, a state machine that specified the pulse durations for each received group, e.g., by incrementing a state that indicates selected signal pulse transition times, a system clock delay chain with multiple taps, a multiplexer controlled by the state machine for successively selecting different taps, and a toggle flip-flop that is clocked by the multiplexer output.
摘要翻译：双相脉冲调制（DPPM）编码器电路将数据转换为一系列高和低信号脉冲，其中每个时间持续时间或脉冲宽度表示一组M个数据位，交替的高和低脉冲表示连续的组。编码器电路可以包括一组并行的串行输出移位寄存器，其将接收到的数据字细分到M位组中，状态机指定每个接收到的组的脉冲持续时间，例如通过递增指示选择的信号脉冲转换时间，具有多个抽头的系统时钟延迟链，由状态机控制的用于连续选择不同抽头的多路复用器，以及由多路复用器输出计时的开关触发器。

88. 发明授权

US06841983B2 Digital signal to pulse converter and method of digital signal to pulse conversion 有权
标题翻译：数字信号脉冲转换器和数字信号到脉冲转换的方法
公开(公告)号：US06841983B2
公开(公告)日：2005-01-11
申请号：US10295539
申请日：2002-11-14
申请人： John Carl Thomas
发明人： John Carl Thomas
IPC分类号： G05F3/26 , H02J7/00 , H02M1/084 , H02M3/156 , H02M3/157 , H02M3/158 , H03M5/08 , G05B24/02
CPC分类号： H02M3/157 , G05F3/262 , H02J7/0065 , H02M1/0845 , H02M3/156 , H02M3/1588 , H02M2001/0012 , H02M2001/007 , H02M2001/008 , H03M5/08 , H05B41/2828 , Y02B20/186 , Y02B70/1466 , Y10T307/438 , Y10T307/469
摘要： A digital signal to pulse converter including a spectral spreader which provides an adjusted clock signal that does not cycle during selected cycles. The adjusted clock signal is written into a multi-port content addressable memory which, as a function of the current count, provides output signals that determine a beginning or an end of a pulse within a frame. The spectral spreader varies the number of selected cycles to adjust the frame rate as desired, linearly or nonlinearly.
摘要翻译：一种数字信号到脉冲转换器，包括频谱扩展器，其提供在选择的周期期间不循环的经调整的时钟信号。经调整的时钟信号被写入多端口内容可寻址存储器，其作为当前计数的函数提供确定帧内的脉冲的开始或结束的输出信号。频谱扩展器根据需要线性或非线性地改变所选周期的数量以调整帧速率。

89. 发明授权

US6133858A Bus system, a peripheral device and a method for decoding a digital signal 失效
标题翻译：总线系统，外围设备和数字信号解码方法
公开(公告)号：US6133858A
公开(公告)日：2000-10-17
申请号：US955060
申请日：1997-10-21
申请人： Otto Karl , Joachim Bauer , Guenther Ott , Dietmar Koehler
发明人： Otto Karl , Joachim Bauer , Guenther Ott , Dietmar Koehler
IPC分类号： H03M5/08 , B60R21/01 , G06F13/42 , H03K9/08 , H04L25/49
CPC分类号： H03K9/08 , G06F13/4286 , B60R2021/01075 , B60R2021/01115
摘要： A method for decoding pulse-width modulated signals, such that a sawtooth signal is generated. The sawtooth signal is synchronized with a signal to be decoded. By comparing the sawtooth signal with a reference, a temporal center of a time period reserved for transmission of a bit can be measured, thus reducing a demodulation of the signal to a measurement of the signal level. Furthermore, a data bus for an activation system utilizing this method is also provided.
摘要翻译：用于解码脉宽调制信号的方法，使得产生锯齿波信号。锯齿波信号与待解码的信号同步。通过将锯齿波信号与参考值进行比较，可以测量保留用于位传输的时间周期的时间中心，从而将信号的解调减小到信号电平的测量值。此外，还提供了一种利用该方法的激活系统的数据总线。

90. 发明授权

US6037884A Technique to encode multiple digital data streams in limited bandwidth for transmission in a single medium 失效
标题翻译：用于在有限带宽内对多个数字数据流进行编码以在单个介质中进行传输的技术
公开(公告)号：US6037884A
公开(公告)日：2000-03-14
申请号：US958184
申请日：1997-10-27
申请人： Barry Thornton
发明人： Barry Thornton
IPC分类号： H04L5/02 , H04L5/22 , H04L25/493 , H03M5/08
CPC分类号： H04L25/493 , H04L5/02 , H04L5/225
摘要： A technique for encoding multiple digital data streams in a limited bandwidth for transmission in a single medium is described. A pulse tuned to an assigned frequency is generated each time a data stream makes a transition. The polarity of each pulse represents the direction of the corresponding transition. In one aspect, a different length pulse is assigned to each incoming data stream to be encoded such that each incoming data stream will generate pulses of different length, thus occupying a different part of the frequency spectrum. These different pulse lengths create a group of "channels" each representing the activities of a different data stream. in each case, the length of the data pulse is shorter than the length of the fastest individual bit to be processed. The pulses are then summed in an analog summer and transmitted as the new, combined data stream.
摘要翻译：描述了用于在有限带宽内编码多个数字数据流以在单个介质中传输的技术。每当数据流进行转换时，产生调整到分配频率的脉冲。每个脉冲的极性表示相应过渡的方向。在一个方面，将不同长度的脉冲分配给要编码的每个输入数据流，使得每个输入数据流将产生不同长度的脉冲，从而占据频谱的不同部分。这些不同的脉冲长度创建一组“通道”，每个“通道”表示不同数据流的活动。在每种情况下，数据脉冲的长度比要处理的最快个别位的长度短。然后将脉冲在模拟夏令时相加并作为新的组合数据流传输。

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