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81. 发明申请

US20030058733A1 Flash memory rewrite circuit, semiconductor integrated circuit, memory card having the semiconductor integrated circuit thereof, method of rewriting flash memory and flash memory rewriting program 有权
标题翻译：闪存重写电路，半导体集成电路，具有其半导体集成电路的存储卡，重写闪速存储器和闪存重写程序的方法
公开(公告)号：US20030058733A1
公开(公告)日：2003-03-27
申请号：US10253531
申请日：2002-09-25
申请人： Kabushiki Kaisha Toshiba.
发明人： Shuzo Mori
IPC分类号： G11C011/34 , G11C016/06 , G11C005/00
CPC分类号： G11C16/105 , G11C16/10 , G11C16/102 , G11C16/3454 , G11C16/3459 , G11C2216/16
摘要： A memory IC card including a card substrate, a semiconductor device mounted on the card substrate, which includes an CPU, a flash memory, a memory block and a flash memory rewrite circuit having a rewrite data control circuit that receives a rewrite instruction of the flash memory from the CPU to store data for a designated byte of a page for rewriting to the memory block, a page data control circuit that sends data of the page excepting the designated byte in the flash memory to the memory block to prepare new page data in the memory block and a data set control circuit that writes the new page data prepared in the memory block to the flash memory; outer terminals mounted on the card substrate; wirings provided on the card substrate to connect the outer terminals.
摘要翻译：一种包括卡片基板，安装在卡片基板上的半导体装置的存储IC卡，其包括CPU，闪速存储器，存储块和具有重写数据控制电路的闪存重写电路，该重写数据控制电路接收闪存的重写指令从CPU存储用于重写到存储器块的页面的指定字节的数据;页数据控制电路，其将除闪存中的指定字节之外的页面的数据发送到存储器块，以准备新的页数据所述存储器块和数据组控制电路将准备在所述存储器块中的新的页数据写入所述闪速存储器; 安装在卡片基板上的外部端子; 设在卡片基板上的布线用于连接外部端子。

82. 发明申请

US20030058692A1 Semiconductor memory and method of controlling the same 有权
公开(公告)号：US20030058692A1
公开(公告)日：2003-03-27
申请号：US10180076
申请日：2002-06-27
申请人： Kabushiki Kaisha Toshiba
发明人： Hitoshi Shiga
IPC分类号： G11C005/00
CPC分类号： G11C16/3445 , G11C5/145 , G11C8/08 , G11C16/12 , G11C16/30 , G11C16/3459
摘要： A semiconductor memory has a memory cell array, a boosted voltage generator to generate a boosted voltage and a decoder to select memory cells in said memory cell array in response to an address signal. The voltage generator is activated in response to input of a first command, and kept active for a period of repeated input of a second command to control for the voltage generator, following the first command. The semiconductor memory may be provided with a regular operation mode in which the voltage generator is controlled to be in an active or inactive state by means of a first command signal in response to a predetermined signal, and a successive operation mode in which the voltage generator is kept active by a second command signal in response to another predetermined signal.

83. 发明申请

US20030058687A1 Semiconductor device 有权
公开(公告)号：US20030058687A1
公开(公告)日：2003-03-27
申请号：US10244489
申请日：2002-09-17
发明人： Hajime Kimura
IPC分类号： G11C011/24 , G11C011/34 , G11C005/00
CPC分类号： H01L27/088 , G09G3/3241 , G09G3/3283 , G09G2300/0426 , G09G2300/0814 , G09G2300/0852 , G09G2300/0861 , G09G2310/0251 , G09G2320/0233 , G09G2320/0252 , H01L27/15
摘要： A light emitting device capable of performing signal electric current write-in operations at high speed and without dispersion in the characteristics of TFTs structuring pixels influencing the brightness of light emitting elements is provided. The gate length L of a transistor in which an electric current flows during write-in of a signal electric current is made shorter than the gate length L of a transistor in which electric current supplied to EL elements flows during light emission, and high speed write-in is thus performed by having a larger electric current flow than the electric current flowing in conventional EL elements. A converter and driver transistor (108) is used for signal write-in. By using the converter and driver transistor (108) and a driver transistor (107) when supplying electric current to a light emitting element during light emission, dispersion in the transistor characteristics can be made to have less influence on brightness than when using a structure in which write-in operations and light emission operations are performed using different transistors.

84. 发明申请

US20030053363A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20030053363A1
公开(公告)日：2003-03-20
申请号：US10235488
申请日：2002-09-06
发明人： Osamu Wada
IPC分类号： G11C005/00
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit comprises an internal potential generation circuit for a memory, a current flow pass interruption circuit connected to the internal potential generation circuit, and an input terminal, connected to the current flow pass interruption circuit, for providing a stand-by setting signal controlling the current flow pass interruption circuit, wherein a potential is supplied to the internal potential generation circuit during the operation of the memory, and it is interrupted during the stand-by of the memory to supply the potential to the internal potential generation circuit.
摘要翻译：半导体集成电路包括用于存储器的内部电位产生电路，连接到内部电位产生电路的电流流通中断电路和连接到电流流通中断电路的输入端子，用于提供待机设置信号控制电流流通中断电路，其中在存储器的操作期间向内部电位产生电路提供电位，并且在存储器的待机期间中断供应到内部电位产生电路的电位。

85. 发明申请

US20030053340A1 DDR sdram for stable read operation 失效
标题翻译： DDR sdram可进行稳定的读取操作
公开(公告)号：US20030053340A1
公开(公告)日：2003-03-20
申请号：US10283535
申请日：2002-10-29
申请人： Hynix Semiconductor Inc.
发明人： Young-Jin Yoon , Kwan-Weon Kim
IPC分类号： G11C005/00
CPC分类号： G11C7/1066 , G11C7/1048 , G11C11/4076 , G11C11/4096
摘要： A global input/output precharge apparatus includes a latch for cross-coupling and latching a global input/output line and a complementary global input/output line; a global input/output line delay for delaying the global input/output line and the complementary global input/output line by a predetermined time delay; a global input/output line precharge logic for pre-charging the global input/output line feed-backed from the global input/output line delay; a first precharge logic for applying a power voltage to the global input/output line when a first logic state is feed-backed on the output of the global input/output line precharge logic and applying a ground voltage to the global input/output line when a second logic state is feed-backed on the output of the global input/output line precharge logic; and a second precharge logic for applying the power voltage to the complementary global input/output line when the first logic state is feed-backed on the output of the global input/output line precharge logic and applying the ground voltage to the complementary global input/output line when the second logic state is feed-backed on the output of the global input/output line precharge logic.
摘要翻译：全局输入/输出预充电装置包括用于交叉耦合和锁存全局输入/输出线和互补的全局输入/输出线的锁存器; 用于将全局输入/输出线和互补的全局输入/输出线延迟预定时间延迟的全局输入/输出线路延迟; 全局输入/输出线预充电逻辑，用于从全局输入/输出线延迟预充电全局输入/输出线; 第一预充电逻辑，用于当在全局输入/输出线预充电逻辑的输出上馈送第一逻辑状态并将全局输入/输出线施加接地电压时，将电源电压施加到全局输入/输出线，在全局输入/输出线预充电逻辑的输出上馈送第二逻辑状态; 以及第二预充电逻辑，用于当第一逻辑状态被馈送到全局输入/输出线预充电逻辑的输出上时将电源电压施加到互补的全局输入/输出线，并将接地电压施加到互补的全局输入/ 当第二逻辑状态在全局输入/输出线预充电逻辑的输出上进行反馈时，输出线路。

86. 发明申请

US20030049912A1 METHOD OF FORMING CHALCOGENIDE COMPRSING DEVICES AND METHOD OF FORMING A PROGRAMMABLE MEMORY CELL OF MEMORY CIRCUITRY 有权
标题翻译：形成混合气压缩装置的方法和形成存储器电路的可编程存储器单元的方法
公开(公告)号：US20030049912A1
公开(公告)日：2003-03-13
申请号：US09943187
申请日：2001-08-29
发明人： Kristy A. Campbell , John T. Moore
IPC分类号： H01L021/06 , H01L021/82 , G11C005/00
CPC分类号： H01L45/1233 , H01L45/04 , H01L45/085 , H01L45/143 , H01L45/1616 , H01L45/1658 , H01L45/1683
摘要： A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing, a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.
摘要翻译：在基板上形成第一导电电极材料。在其上形成包含硫属元素的材料。硫族化物材料包括AxSey。在硫族化物材料上形成含银层。银被照射有效地破坏硫族化物材料在含银层和硫族化物材料的界面处的硫属化物键，并将至少一些银扩散到硫族化物材料中。在照射之后，硫族化物材料外表面暴露于含有碘的流体，其有效地减少硫族化物材料外表面的暴露之前的粗糙度。曝光后，将第二导电电极材料沉积在硫族化物材料上，并且至少在硫族化物材料上连续并完全覆盖，并且将第二导电电极材料形成为器件的电极。

87. 发明申请

US20030043680A1 Semiconductor memory circuit 有权
标题翻译：半导体存储电路
公开(公告)号：US20030043680A1
公开(公告)日：2003-03-06
申请号：US10190480
申请日：2002-07-09
申请人： Hitachi, Ltd.
发明人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C005/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译：本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。

88. 发明申请

US20030039164A1 Intermediate boosted array voltage 有权
标题翻译：中间升压阵列电压
公开(公告)号：US20030039164A1
公开(公告)日：2003-02-27
申请号：US09934969
申请日：2001-08-22
发明人： Troy Manning
IPC分类号： G11C005/00
CPC分类号： H02M3/07 , G11C5/145
摘要： The present invention provides two voltage pumps, or a single voltage pump having two pump circuits, with one pump or pump circuit having as its target value the normal pumped voltage and the other pump or pump circuit having as its target value an intermediate pumped voltage which is less than the normal pumped voltage but still greater than the supply voltage. The intermediate pumped voltage may be used quite effectively for signals such as Bias, EQ, ISO, or at any other point on the die that needs a pumped voltage, but not a pumped voltage as high as the voltage that the access devices require. The bus used to route the pumped voltage may be split to enable both the pumped voltage and the intermediate pumped voltage to be routed without requiring an additional bus or changes to existing masks. Methods of operating multiple voltage pumps and supplying a full pumped voltage and an intermediate pumped voltage are also disclosed.
摘要翻译：本发明提供了两个电压泵或具有两个泵电路的单电压泵，其中一个泵或泵电路具有作为其正常泵浦电压的目标值，另一个泵或泵电路具有作为其目标值的中间泵送电压，小于正常的泵浦电压，但仍大于电源电压。中间泵浦电压可以非常有效地用于诸如Bias，EQ，ISO之类的信号，或在需要泵浦电压的芯片上的任何其他点，而不是与接入设备所需的电压一样高的泵浦电压。用于路由泵浦电压的总线可以被分开，以使泵浦电压和中间泵送电压都能被路由，而不需要额外的总线或改变现有的掩模。还公开了操作多个电压泵并提供全泵浦电压和中间泵送电压的方法。

89. 发明申请

US20030021164A1 Semiconductor memory device having different data rates in read operation and write operation 失效
公开(公告)号：US20030021164A1
公开(公告)日：2003-01-30
申请号：US10246744
申请日：2002-09-19
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Chang-sik Yoo , Tae-sung Jung
IPC分类号： G11C007/00 , G11C008/00 , G11C005/00
CPC分类号： G11C7/22 , G11C7/1051
摘要： A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.

90. 发明申请

US20030021159A1 Compact analog-multiplexed global sense amplifier for rams 有权
标题翻译：紧凑型模拟多路复用全局读出放大器
公开(公告)号：US20030021159A1
公开(公告)日：2003-01-30
申请号：US10224841
申请日：2002-08-21
申请人： Broadcom Corporation
发明人： Sami Issa
IPC分类号： G11C005/00
CPC分类号： G11C11/4097 , G11C7/1006 , G11C7/12 , G11C7/18 , G11C2207/002 , G11C2207/104
摘要： The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a result, the respective local sense amplifiers for the non-selected global bit lines will just read and refresh the respective memory cells. This new approach results in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and multiplexed to achieve the advantages of the present invention. Due to an analog global multiplexing scheme used by the present invention, only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. The global bit line pairs with no voltage development generate zero voltage development on the local bit lines and the respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.
摘要翻译：本发明的方法和系统通过将未选择的全局位线连接到Vdd来叠加读写操作。结果，用于非选择的全局位线的各个本地读出放大器将仅读取和刷新相应的存储器单元。这种新方法导致较小的本地读出放大器和一个用于多个存储器单元（和局部读出放大器）的全局读出放大器。在一个实施例中，八个全局位线由一个全局读出放大器共享并被多路复用以实现本发明的优点。由于本发明使用的模拟全局复用方案，在写入操作期间，只有一个全局位线对产生作为相应局部读出放大器的输入的电压开发，而另外三个全局位线对与它们各自的本地感测放大器，因此没有电压发展。没有电压开发的全局位线对在局部位线上产生零电压显影，并且相应的激活的读出放大器仅放大重新组合读取和刷新操作的单元数据。

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