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    • 82. 发明专利
    • FREQUENCY MEASURING DEVICE
    • JPH04248471A
    • 1992-09-03
    • JP3338291
    • 1991-02-04
    • MITSUBISHI ELECTRIC CORP
    • HAMADA YOSHIO
    • G01R23/175H03D3/00
    • PURPOSE:To enable frequency to be measured even in a wide frequency range by providing an equalizer with certain frequency characteristics at a previous stage of a phase discrimination circuit and a detection circuit of a video amplitude data which is determined by frequency characteristics at a later stage and determing frequency from the data and I/Q video quantized output. CONSTITUTION:An RF signal passed through an equalizer 10 with certain frequency characteristics and is fed to an I/Q phase discrimination circuit 5. An output QA of an adder 11 can detect a video amplitude which is determined by frequency characteristics of the equalizer 10. The video amplitude signal is converted to a quantized amplitude data, thus enabling ranges A and B of frequency measurement to be determined. A polarity is judged by a frequency calculation circuit 13 according to this amplitude data and an I/Q video, is code-converted, and is outputted as a digital data, thus enabling an uncertainty of a frequency precise measurement system of the I/Q video system to be compensated for by a rough measurement system of the amplitude data system and obtaining a high resolution.
    • 84. 发明专利
    • SIMULTANEOUS DELAY CORRELATOR
    • JPH01232271A
    • 1989-09-18
    • JP33278588
    • 1988-12-28
    • HUGHES AIRCRAFT CO
    • REYNOLDS SAMUEL CCHANG DONALD C D
    • G01R29/00G01R23/163G01R23/175H01P5/16
    • PURPOSE: To obtain a small and simple simultaneous delay correlation unit in which configuration and arrangement are facilitated by delaying two input signals simultaneously using a single transmission line and connecting two input signals with the opposite end parts of transmission line. CONSTITUTION: A single transmission line 17 is used for delaying a first and second input signals simultaneously. Circulators 19, 21 are arranged at the opposite end of the line 17 and one circulator 19 receives a first input signal transmitted on a line 23 and delivers the received signal in one direction while coupling the signals with the line. At the same time, the other circulator 21 receives a second input signal transmitted on a line 24 and delivers the received signal in the opposite direction while coupling the signal with the line. Each circulator 19, 21 is associated with an appropriate matching load terminal. A plurality of directional couplers 27a-27i are arranged at an interval along the line 17 and the output the delayed version of first and second input signals transmitted in the opposite directions along the line.
    • 85. 发明专利
    • CHIRP CONVERTER
    • JPS61294376A
    • 1986-12-25
    • JP13575785
    • 1985-06-21
    • NEC CORP
    • UEDA ISAMU
    • G06G7/19G01R23/175
    • PURPOSE:To simplify a device by making common use of a 90 deg. hybrid mixer and chirp signal generator for modulation and demodulation. CONSTITUTION:The 90 deg. hybride mixer 4 and the chirp signal generator 1 are commonly used for modulation and demodulation by changing over of switch circuits 2, 6, 10. Two input signals of I, Q are inputted to the mixers 3, 5 during the modulation operation. The input signals are modulated by the signal from the generator 1 in which the phase is divided to two components different from each other by 90 deg. and thereafter the signals are synthesized by the hybrid 8. The synthesized signal is inputted to DDL11. The switches 2, 6, 10 are changed over upon the completion of inputting so that the demodulation operation is started. More specifically, the output from the DDL11 is branched by the hybrid 8 and is inputted to the mixers 3, 5. The mixers 3, 5 demodulate the input signals with the same signal as in the modulation stage and output the signals to higher harmonic wave removing filters 7, 9.
    • 87. 发明专利
    • Z CONVERTER OF ACOUSTIC SURFACE WAVE CHIRP
    • JPS58155477A
    • 1983-09-16
    • JP3855882
    • 1982-03-11
    • NIPPON ELECTRIC CO
    • KITANO TOSHIHIKO
    • H03H9/64G01R23/175G06F17/14G06F17/15G06G7/19H03H3/08H03H9/44
    • PURPOSE:To make the in-band amplitude characteristic flat to improve the conversion precision, by using three acoustic surface wave dispersing delay lines different in delay characteristic to perform the Fourier transform of an input signal. CONSTITUTION:Pulses from an RF pulse generator 2 are applied to an acoustic surface wave dispersing delay line 1 having the characteristic, where the delay time is shortened linearly for the frequency, to obtain a chirp signal. A composite signal obtained by multiplying this chirp signal and a signal r(t) having an unknown frequency spectrum in a multiplexer 3 is applied to an acoustic surface wave dispersing delay line 4 having the Characteristic where the delay time is extended for the frequency. The output of this delay line 4 and a chirp signal obtained in an acoustic surface wave dispersing delay line 5 having the same characteristic as the delay line 1 are multiplied in a multiplexer 7 to obtain a Fourier transform signal of the signal r(t). In this case, the width and the carrier frequency of input pulses of the delay line 5 are controlled to eliminate the influence of the amplitude inclination of the delay line upon an output signal S(tau).
    • 89. 发明专利
    • DIGITIZING INSTANTANEOUS FREQUENCY MEASURING DEVICE
    • JPS57207869A
    • 1982-12-20
    • JP9427581
    • 1981-06-17
    • MITSUBISHI ELECTRIC CORP
    • MINAMI NAOYUKI
    • G01R23/175G01R23/02
    • PURPOSE:To use an I/Q phase discriminating circuit in common, to make a device small-sized, and also to elevate a frequency measuring accuracy, by switching and selecting plural delay signal whose delay time is different from each other, and inputting its selected signal to one I/Q phase discriminating circuit. CONSTITUTION:An inputted high frequency signal is distributed in phase, one input signal 15 is inputted to an I/Q phase discriminating circuit 6, and the other input signal is delayed by delaying circuits 5a-5c, respectively, and becomes delay signals 16a-16c, respectively. A switching circuit 41 switches the signals 16a-16c by a control signal generated by a timing pulse generation controlling circuit 42, in accordance with an arrival time of the input signal, and a delay signal 16 is is obtained. When this signal 16 is inputted to the I/Q phase discriminating circuit 6 and phase synthesis is executed between this signal and said non-delay signal 15, I and Q video outputs whose 1 period becomes 1/gamma, 1/2gamma-1/ngamma against input carrier frequency at every changeover of the switch are obtained.