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81. 发明授权

US07358884B1 Methods and systems for implementing a Digital-to-Analog Converter 有权
标题翻译：用于实现数模转换器的方法和系统
公开(公告)号：US07358884B1
公开(公告)日：2008-04-15
申请号：US11544489
申请日：2006-10-05
申请人： Lawrence Frederick Heyl , David Tupman , Brian A. Childers
发明人： Lawrence Frederick Heyl , David Tupman , Brian A. Childers
IPC分类号： H03M1/66
CPC分类号： H03M3/376 , H03H17/0292 , H03H17/0416 , H03H17/0607 , H03H17/0621 , H03H2218/085 , H03M3/32 , H03M3/424 , H03M3/436 , H03M3/506 , H03M3/508 , H03M3/51 , H03M7/3026 , H03M7/3042
摘要： A self-contained DAC that is especially suitable for use as an IP core, particularly for SOC (System on Chip) implementation. Techniques are applied to employ certain circuits (such as arithmetic element 302) to perform multiple functions in the DAC, thereby resulting in space saving. Techniques are also applied to employ fewer circuits per functional block to achieve further space saving. By employing multiple clock domains and turning on selective circuits on an as-needed basis, power saving is also realized.
摘要翻译：一个独立的DAC，特别适用于IP核，特别适用于SOC（片上系统）。应用技术来采用某些电路（例如算术元件302）在DAC中执行多个功能，从而节省空间。技术也被应用于每个功能块采用更少的电路以实现进一步的空间节省。通过采用多个时钟域并根据需要开启选择电路，也实现了省电。

82. 发明授权

US07358879B2 ΔΣ modulator system with start up transient suppression 有权
标题翻译： DeltaSigma调制器系统启动瞬态抑制
公开(公告)号：US07358879B2
公开(公告)日：2008-04-15
申请号：US11493415
申请日：2006-07-26
申请人： Richard Schreier , Nazmy Abaskharoun
发明人： Richard Schreier , Nazmy Abaskharoun
IPC分类号： H03M3/00
CPC分类号： H03M3/376 , H03M3/458
摘要： A ΔΣ modulator system with start up transient suppression includes a ΔΣ analog to digital converter having predetermined internal signal limits; an envelope control circuit for attenuating the input signal to the ΔΣ analog to digital converter and a control circuit responsive to a start/reset signal to enable for a limited time the envelope control circuit to attenuate the input signal to maintain the ΔΣ analog to digital converter internal signal substantially within the predetermined internal signal limits.
摘要翻译：具有启动瞬态抑制的DeltaSigma调制器系统包括具有预定内部信号限制的DeltaSigma模数转换器; 用于衰减到DeltaSigma模数转换器的输入信号的包络控制电路和响应于启动/复位信号的控制电路，以在限定的时间内使包络线控制电路衰减输入信号以维持DeltaSigma模数转换器内部信号基本上在预定的内部信号限制内。

83. 发明申请

US20080084343A1 METHODS AND SYSTEMS FOR IMPLEMENTING A DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：用于实现数字到模拟转换器的方法和系统
公开(公告)号：US20080084343A1
公开(公告)日：2008-04-10
申请号：US11544489
申请日：2006-10-05
申请人： Lawrence Frederick Heyl , David Tupman , Brian A. Childers
发明人： Lawrence Frederick Heyl , David Tupman , Brian A. Childers
IPC分类号： H03M1/66
CPC分类号： H03M3/376 , H03H17/0292 , H03H17/0416 , H03H17/0607 , H03H17/0621 , H03H2218/085 , H03M3/32 , H03M3/424 , H03M3/436 , H03M3/506 , H03M3/508 , H03M3/51 , H03M7/3026 , H03M7/3042
摘要： A self-contained DAC that is especially suitable for use as an IP core, particularly for SOC (System on Chip) implementation. Techniques are applied to employ certain circuits (such as arithmetic element 302) to perform multiple functions in the DAC, thereby resulting in space saving. Techniques are also applied to employ fewer circuits per functional block to achieve further space saving. By employing multiple clock domains and turning on selective circuits on an as-needed basis, power saving is also realized.
摘要翻译：一个独立的DAC，特别适用于IP核，特别适用于SOC（片上系统）。应用技术来采用某些电路（例如算术元件302）在DAC中执行多个功能，从而节省空间。技术也被应用于每个功能块采用更少的电路以实现进一步的空间节省。通过采用多个时钟域并根据需要开启选择电路，也实现了省电。

84. 发明申请

US20070152857A1 DELTA-SIGMA DAC 有权
公开(公告)号：US20070152857A1
公开(公告)日：2007-07-05
申请号：US11609477
申请日：2006-12-12
申请人： Wei-Hsuan Tu , Tse-Hsiang Hsu
发明人： Wei-Hsuan Tu , Tse-Hsiang Hsu
IPC分类号： H03M3/00
CPC分类号： H03M3/346 , H03M3/376 , H03M3/502 , H03M3/504
摘要： A Delta-Sigma DAC is provided, comprising an interpolator, a Delta-Sigma modulator, a FIR filter and an analog filter. The interpolator oversamples a n-bit digital signal to generate a n-bit oversampled signal. The Delta-Sigma modulator coupled to the output of interpolator shapes the n-bit oversampled digital signal to generate a shaped digital signal. The FIR filter coupled to the Delta-Sigma modulator filters the shaped digital signal to generate an analog audio signal. The analog filter coupled to the FIR filter amplifies the analog audio signal to generate a audible signal.
摘要翻译：提供了一种Delta-Sigma DAC，包括内插器，Δ-Σ调制器，FIR滤波器和模拟滤波器。内插器过采样n位数字信号以产生n位过采样信号。耦合到内插器的输出的Δ-Σ调制器对n位过采样的数字信号进行整形，以产生成形的数字信号。耦合到Δ-Σ调制器的FIR滤波器对形状的数字信号进行滤波以产生模拟音频信号。耦合到FIR滤波器的模拟滤波器放大模拟音频信号以产生可听信号。

85. 发明申请

US20040130472A1 Pulse width modulation digital amplifier 失效
标题翻译：脉宽调制数字放大器
公开(公告)号：US20040130472A1
公开(公告)日：2004-07-08
申请号：US10740754
申请日：2003-12-22
申请人： Renesas Technology Corp.
发明人： Masako Arizumi , Hiroyuki Harada
IPC分类号： H03M001/82
CPC分类号： H03F3/217 , H03M1/0872 , H03M1/822 , H03M3/376 , H03M3/506
摘要： In a digital amplifier, a time controller generates first and second selection signals for outputting any one of music data, a center output, and a lowest output to a P output and an N output based on a power ON/OFF signal and a start/stop signal, and also generates a third selection signal for determining whether a signal having the same phase as that of the P output is output to the N output or a signal obtained by inverting the P output is output to the N output. A data selection circuit determines data to be output to the P output and the N output based on the first and second selection signals. An output data register circuit converts parallel data determined by the data selection circuit into serial data to output the serial data into the P output. An output selection circuit determines the N output based on the third selection signal.
摘要翻译：在数字放大器中，时间控制器产生用于将音频数据，中心输出和最低输出中的任何一个输出到P输出和N输出的第一和第二选择信号，其基于电源ON / OFF信号和开始/ 并且还产生用于确定与P输出具有相同相位的信号是否被输出到N输出的第三选择信号或者通过将P输出反相获得的信号被输出到N输出。数据选择电路基于第一和第二选择信号确定要输出到P输出和N输出的数据。输出数据寄存器电路将由数据选择电路确定的并行数据转换成串行数据，将串行数据输出到P输出。输出选择电路根据第三选择信号确定N输出。

86. 发明授权

US6118399A Coarse/fine switching on digital-to-analog conversion output 失效
标题翻译：粗/精切换数模转换输出
公开(公告)号：US6118399A
公开(公告)日：2000-09-12
申请号：US50590
申请日：1998-03-30
申请人： Andrew W. Krone
发明人： Andrew W. Krone
IPC分类号： H03M3/02 , H03M1/68
CPC分类号： H03M3/376 , H03F1/3211 , H03F3/45475 , H03H19/004 , H03F2203/45514 , H03M3/502
摘要： A technique for providing coarse and fine switching on digital-to-analog converter output for a more refined analog output signal. In a digital-to-analog converter utilizing a switched capacitor low-pass filter, the last stage of the filter implements a two phase charging scheme to ensure distortion reduction.
摘要翻译：一种用于在数模转换器输出端提供粗调和精细开关的技术，用于更精细的模拟输出信号。在使用开关电容器低通滤波器的数模转换器中，滤波器的最后一级实现了两相充电方案，以确保失真减小。

87. 发明授权

US5754131A Low power delta sigma converter 失效
标题翻译：低功率Δ-Σ转换器
公开(公告)号：US5754131A
公开(公告)日：1998-05-19
申请号：US673543
申请日：1996-07-01
申请人： David Byrd Ribner , Juha Mikko Hakkarainen , David Henry Kenneth Hoe
发明人： David Byrd Ribner , Juha Mikko Hakkarainen , David Henry Kenneth Hoe
IPC分类号： H03M3/02 , H03M3/00
CPC分类号： H03M3/32 , H03M3/376 , H03M3/43
摘要： A delta sigma modulator that has a low power dissipation without sacrificing modulator resolution includes, in one embodiment, a current mode digital to analog converter (DAC) in shunt with a conventional op amp in the first stage of the delta sigma modulator. By adding the current mode DAC in shunt with the first (or only) stage op amp of the delta sigma modulator, the slewing current needed during transients is provided by the combination of the op amp and DAC output signals. Since the DAC provides the slewing current required for the output signal change, the op amp need not apply the slewing current and therefore need only operate at low quiescent power.
摘要翻译：在一个实施例中，具有低功耗而不牺牲调制器分辨率的ΔΣ调制器包括与ΔΣ调制器的第一级中的常规运算放大器分流的电流模式数模转换器（DAC）。通过将电流模式DAC与Δ-Σ调制器的第一（或仅））级运算放大器并联，瞬态期间所需的回转电流由运算放大器和DAC输出信号的组合提供。由于DAC提供输出信号变化所需的回转电流，因此运算放大器不需要使用回转电流，因此只需要在低静态功率下工作。

88. 发明公开

EP3119001A1 A SIGMA-DELTA MODULATOR 有权
标题翻译： SIGMA-DELTA调制器
公开(公告)号：EP3119001A1
公开(公告)日：2017-01-18
申请号：EP15176685.4
申请日：2015-07-14
申请人： NXP B.V.
发明人： Breems,, Lucien Johannes , Bolatkale,, Muhammed
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M3/376 , H03M3/42 , H03M3/452 , H03M3/454 , H03M3/464 , H03M3/50
摘要： A sigma-delta modulator (300) comprising a plurality of filter stages (328) in series with each other, wherein at least one of the plurality of filter stages (328) is configured to provide a filter-output-signal; and a plurality of gain stages (330), each gain stage (330) configured to provide a gain-output-signal. The sigma-delta modulator (300) also includes a filter-output-switching-element (352) configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages (330); and a plurality of filter-input-switching-elements (354, 356, 358, 360). Each of the plurality of filter-input-switching-elements (354, 356, 358, 360) is associated with one of the plurality of filter stages (328), wherein the plurality of filter-input-switching-elements (354, 356, 358, 360) are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages (328).
摘要翻译：包括彼此串联的多个滤波器级（328）的Σ-Δ调制器（300），其中所述多个滤波器级（328）中的至少一个被配置为提供滤波器输出信号; 和多个增益级（330），每个增益级（330）被配置为提供增益 - 输出信号。 Σ-Δ调制器（300）还包括滤波器输出开关元件（352），其被配置为选择性地将滤波器输出信号耦合到多个增益级之一的输入端; 和多个滤波器输入开关元件（354,356,358,360）。多个滤波器输入开关元件（354,356,358,360）中的每一个与多个滤波器级（328）中的一个相关联，其中多个滤波器输入开关元件（354,356 ，358,360）被配置为选择性地将所述增益级输出信号之一耦合到所述多个滤波器级（328）中的相关联的一个的输入端。

89. 发明授权

EP2365634B1 Pulse density modulation method and apparatus 有权
标题翻译：脉冲密度调制方法和装置
公开(公告)号：EP2365634B1
公开(公告)日：2016-12-21
申请号：EP10156140.5
申请日：2010-03-10
申请人： NXP B.V.
发明人： Dooper, Lûtsen Ludgerus Albertus Hendrikus
IPC分类号： H03M3/02
CPC分类号： H03M3/376 , H03M3/50

90. 发明授权

EP0998795B1 METHOD AND APPARATUS FOR PERFORMANCE IMPROVEMENT BY QUALIFYING PULSES IN AN OVERSAMPLED, NOISE-SHAPING SIGNAL PROCESSOR 失效
标题翻译：提高性能的凭资质IN A脉冲的方法和装置的过采样噪声整形信号处理器
公开(公告)号：EP0998795B1
公开(公告)日：2006-02-22
申请号：EP98937027.5
申请日：1998-07-20
申请人： Tripath Technology, Inc.
发明人： TRIPATHI, Adya, S. , DELANO, Cary, L.
IPC分类号： H04B14/06
CPC分类号： H04B14/06 , H03M3/376 , H03M3/43 , H03M3/454
摘要： An oversampled, noise shaping signal processor (300) is described having at least one integrator stage (306) in the loop. A sampling stage (310) is connected coupled to the at least one integrator stage. The sampling stage samples an analog signal at a sample frequency. Qualification logic (318) coupled to the sampling stage receives a pulse waveform therefrom, and ensures that signal transitions in the pulse waveform occur more than a first time period apart and that the waveform can therefore be handled by, for example, a power switching device (312). A switching stage (312) in the loop is coupled to the qualification logic. The signal processor (300) has a feedback path from the output of the switching stage (312) to the input of the at least one integrator stage (306) thereby closing the loop.

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