专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

EP2187525B1 ERROR DETECTION DEVICE, AND ERROR CORRECTION/ERROR DETECTION DECODING DEVICE AND METHOD 有权
标题翻译：错误检测器和纠错/检测解码装置和方法
公开(公告)号：EP2187525B1
公开(公告)日：2014-03-12
申请号：EP07792110.4
申请日：2007-08-07
申请人： Fujitsu Limited
发明人： IKEDA, Norihiro
IPC分类号： H03M13/09 , H04L1/00
CPC分类号： H03M13/093 , H03M13/09

82. 发明公开

EP2187525A1 ERROR DETECTION DEVICE, AND ERROR CORRECTION/ERROR DETECTION DECODING DEVICE AND METHOD 有权
标题翻译： FEHLERDETEKTIONSEINRICHTUNG UND FEHLERKORREKTUR- / FEHLERDETEKTIONSDEKODIERUNGSEINRICHTUNG UND VERFAHREN
公开(公告)号：EP2187525A1
公开(公告)日：2010-05-19
申请号：EP07792110.4
申请日：2007-08-07
申请人： Fujitsu Limited
发明人： IKEDA, Norihiro
IPC分类号： H03M13/09 , H04L1/00
CPC分类号： H03M13/093 , H03M13/09
摘要： Disclosed is an error detection method that detects whether or not there is error in input data sequence wherein the input data sequence is created at an encoder by regarding a data sequence having a specified bit length as a polynomial, dividing that polynomial by a generator polynomial for generating error detection code adding the error detection code to the data sequence so that the remainder becomes '0'. This error detection method comprises: a step of calculating remainder values by dividing polynomials that correspond to each respective bit position by the generator polynomial and saving those remainder values beforehand in a memory; a step of inputting together with an input data sequence bit position information that indicates the proper bit position of each data of the input data sequence, a step of finding from the memory remainder values that correspond to the proper bit positions of data of the input data sequence that are not '0', and performing bit-corresponding addition of each of the found remainder values; and a step of determining that there is no error in the input data sequence when all of the bits of the addition result become '0', and otherwise determining that there is error.
摘要翻译：公开了一种错误检测方法，其检测输入数据序列中是否存在错误，其中通过将具有指定位长度的数据序列相关联作为多项式，在编码器处创建输入数据序列，将该多项式除以生成多项式，产生将错误检测码添加到数据序列的错误检测码，使得余数变为“0”。该错误检测方法包括：通过将与各个比特位置相对应的多项式除以生成多项式并将这些余数值预先保存在存储器中来计算余数值的步骤; 与指示输入数据序列的每个数据的适当位位置的输入数据序列位位置信息一起输入的步骤，从存储器发现与输入数据的数据的适当位位置相对应的余数值的步骤不是'0'的序列，并且执行每个找到的余数值的比特对应的相加; 以及当相加结果的所有位变为“0”时确定输入数据序列中没有错误的步骤，否则确定存在错误。

83. 发明公开

EP2175559A1 Error-detecting decoder with re-calculation of a remainder upon partial re-transmission of a data string. 审中-公开
标题翻译：错误检测解码器重新计算的数据序列的部分重传之后的除法的余数
公开(公告)号：EP2175559A1
公开(公告)日：2010-04-14
申请号：EP10150593.1
申请日：2002-04-22
申请人： Fujitsu Limited
发明人： Obuchi, Kazuhisa , Yano, Tetsuya , Nakamura, Takaharu
IPC分类号： H03M13/09 , H04L1/00
CPC分类号： H03M13/091 , H03M13/093 , H04L1/0043 , H04L1/0061 , H04L1/1829
摘要： Disclosed are an error-detecting encoding apparatus for creating parity bits by error-detecting encoding processing, appending the parity bits to an input data string and encoding the data string, and an error-detecting decoding apparatus for detecting error using these parity bits. Data segmenting means segments an input data string, which is to undergo error-detecting encoding, into a plurality of sub-data strings, dividing means divides the segmented sub-data strings by a polynomial, which is for generating an error-detecting code, and calculates remainders, converting means applies conversion processing, which conforms to a segmentation position of the sub-data strings, to the remainders on a per-remainder basis, and combining means combines converted values, which have been obtained by the conversion processing, and outputs parity bits. An encoder appends this parity to a data string, and a decoder detects error using this parity.
摘要翻译：本发明公开了在用于通过检错编码处理产生的奇偶校验位，并附加奇偶校验位来对输入数据串和编码的数据串的错误检测编码装置，在使用这些奇偶校验位检测错误的检错解码装置。数据分割装置输入数据串的段，所有这些是经过检错编码，成子数据串的复数，划分装置的一个多项式除以分割的子数据串，所有这些是在错误检测码生成，并计算余数，转换装置施加转换处理，符合所述子数据串的分割位置，以在每个剩余基余数，和组合装置转换后的值，其已经获得通过转换处理，并输出奇偶校验比特。编码器本奇偶校验数据附加到一个字符串，和一个解码器使用该奇偶校验检测误差。

84. 发明公开

EP1499024A1 ERROR-DETECTION ENCODER AND DECODER, AND DIVISOR 有权
标题翻译：错误检测编码器和解码器，以及DIVISOR
公开(公告)号：EP1499024A1
公开(公告)日：2005-01-19
申请号：EP02720542.6
申请日：2002-04-22
申请人： FUJITSU LIMITED
发明人： OBUCHI, Kazuhisa , YANO, Tetsuya , NAKAMURA, Takaharu
IPC分类号： H03M13/15 , H04L1/00
CPC分类号： H03M13/091 , H03M13/093 , H04L1/0043 , H04L1/0061 , H04L1/1829
摘要： Disclosed are an error-detecting encoding apparatus for creating parity bits by error-detecting encoding processing, appending the parity bits to an input data string and encoding the data string, and an error-detecting decoding apparatus for detecting error using these parity bits. Data segmenting means segments an input data string, which is to undergo error-detecting encoding, into a plurality of sub-data strings, dividing means divides the segmented sub-data strings by a polynomial, which is for generating an error-detecting code, and calculates remainders, converting means applies conversion processing, which conforms to a segmentation position of the sub-data strings, to the remainders on a per-remainder basis, and combining means combines converted values, which have been obtained by the conversion processing, and outputs parity bits. An encoder appends this parity to a data string, and a decoder detects error using this parity.
摘要翻译：本发明公开了一种用于通过错误检测编码处理来创建奇偶校验位，将奇偶校验位附加到输入数据串并对数据串进行编码的错误检测编码设备以及一种使用这些奇偶校验位来检测错误的错误检测解码设备。数据分割装置将要进行检错编码的输入数据串分割成多个子数据串，分割装置用多项式分割分割后的子数据串，该多项式用于产生检错码，并且计算余数，转换装置按照每个余数将基于子数据串的分段位置的转换处理应用到余数，并且组合装置组合转换处理获得的转换值，以及输出奇偶校验位。编码器将该奇偶校验附加到数据串，并且解码器使用该奇偶校验检测错误。

85. 发明授权

EP1154576B1 Error detection scheme for ARQ systems 失效
标题翻译：错误检测ARQ系统
公开(公告)号：EP1154576B1
公开(公告)日：2004-01-21
申请号：EP01119646.6
申请日：1997-09-22
申请人： Ericsson, Inc.
发明人： Irvin, David R. , Khayrallah, Ali S.
IPC分类号： H03M13/00 , H04L1/18
CPC分类号： H03M13/093 , G11B20/1803 , H04L1/0001 , H04L1/1628 , H04L1/18 , H04L1/1806 , H04L1/1809 , H04L1/1812 , H04L1/1838 , H04L1/1845 , H04L1/1877 , H04L1/188 , H04L2001/0093

86. 发明授权

EP0928520B1 ERROR DETECTION SCHEME FOR ARQ SYSTEMS 失效
标题翻译：法故障检测系统自动重复请求
公开(公告)号：EP0928520B1
公开(公告)日：2002-11-27
申请号：EP97942637.6
申请日：1997-09-22
申请人： Ericsson, Inc.
发明人： IRVIN, David, R. , KHAYRALLAH, Ali, S.
IPC分类号： H03M13/00 , H04L1/18
CPC分类号： H03M13/093 , G11B20/1803 , H04L1/0001 , H04L1/1628 , H04L1/18 , H04L1/1806 , H04L1/1809 , H04L1/1812 , H04L1/1838 , H04L1/1845 , H04L1/1877 , H04L1/188 , H04L2001/0093

87. 发明公开

EP0735711A1 Method and apparatus for modifying a frame check sequence (FCS) 失效
标题翻译： Verfahren und Anordnung zur Modifizierung vonRahmenprüfmusterfolgen（FCS）
公开(公告)号：EP0735711A1
公开(公告)日：1996-10-02
申请号：EP95480032.2
申请日：1995-03-31
申请人： International Business Machines Corporation
发明人： Glaise, René
IPC分类号： H04L1/00 , H03M13/00 , H04L7/04 , H04L12/56
CPC分类号： H03M13/093 , H04L1/0083 , H04L2012/5647 , H04Q11/0478
摘要： In the intermediate network nodes of the high speed packet switching networks, when a message is modified, the invention proposes a method and an apparatus to calculate the modified FCS error code. Using the properties of calculations in the Galois Field, the implementation of the invention, specially in the intermediate Frame Relay network nodes, consists in implementing the following steps and m being the distance from the last bit of the modified filed of the message to the Least Significant Bit of the message including the FCS bits:

splitting the bit stream representing m into a plurality of bits streams;
building a plurality of tables comprising the possible elements of the Galois Field generated by the generator polynomial G of the error code; each table corresponding to all the possible values of the bits streams coming from the splitting of the m bits stream;
for each bits field, pointing in each corresponding lookup table to the corresponding element in the Galois Field;
starting with the LSB bits fields, performing recurrent multiplications in the Galois Field of a Galois Field element found in a lookup table with the Galois Field element found in the previous lookup table;
determining in the data stored to the element in the Galois Field αm corresponding to m;
Calculating the delta vector resulting in the difference between the initial and the final bits stream messages not including the FCS bits;
calculating the remainder in the division by the generator polynomial of the delta vector; if the length of the modified bits field is smaller than the degree of G, the remainder being the delta vector itself; performing a Galois Field multiplication of the result of the previous step with said remainder;
adding the result of the previous step with the initial error code, the result being the final error code which is the error code of the modified message.
摘要翻译：在高速分组交换网络的中间网络节点中，当消息被修改时，本发明提出了一种计算修改的FCS错误码的方法和装置。使用伽罗瓦域中的计算属性，特别是在中间帧中继网络节点中实施本发明在于实现以下步骤，m是从修改的消息字段的最后一位到最小的距离包括FCS位的消息的有效位：将表示m的比特流分解成多个比特流; 构建多个表，其包括由所述错误代码的生成多项式G产生的伽罗瓦域的可能元素; 每个表对应于来自m比特流的分裂的比特流的所有可能值; 对于每个比特字段，将每个对应的查找表指向伽罗瓦域中的相应元素; 从LSB比特字段开始，在查找表中发现的伽罗瓦域元素的伽罗瓦域中执行与先前查找表中发现的伽罗瓦域元素的循环乘法; 确定存储在对应于m的伽罗瓦域αm中的元素的数据; 计算导数不包括FCS比特的初始和最终比特流消息之间差异的增量向量; 通过delta向量的生成多项式计算除法中的余数; 如果修改的比特字段的长度小于G的程度，则余数为增量矢量本身; 执行前一步骤的结果与所述余数的伽罗瓦域乘法; 将上一步的结果与初始错误代码相加，结果为最终错误代码，即修改消息的错误代码。

88. 发明公开

EP0681381A1 Method and apparatus for modifying frame check sequences in intermediate high speed network nodes 失效
标题翻译：方法和装置的高速网络的中间节点的帧控制字的修改。
公开(公告)号：EP0681381A1
公开(公告)日：1995-11-08
申请号：EP94480036.6
申请日：1994-05-06
申请人： International Business Machines Corporation
发明人： Galand, Claude , Spagnol, Victor , Saint-Georges, Eric
IPC分类号： H04L1/00 , H03M13/00 , H04L7/04 , H04L12/56
CPC分类号： H03M13/093 , H04L1/0083 , H04L7/048 , H04L12/56 , H04L2012/5673 , H04L2012/5674
摘要： A method and an apparatus to calculate in an intermediate node of a communication network, the new Frame Check Sequence (FCS) appended to a data bits message which has been modified in said intermediate network node. The invention is useful for high speed networks where the transit delay needs to be optimized in the network along with the computing resources in the intermediate network nodes in terms of computer cycles and memory size.
The invention consists in calculating the difference between the FCS using the difference between the modified fields in the message and the distance in bits between the end of the modified field and the end of the message; the calculation consists in differentiating 'short messages' in the data flow and to provide an optimized processing for the short messages, the processing for larger messages being based on this first optimized processing.
The calculation of the modified FCS comprises operations on polynomials whose coefficients belong to the Galois's Field and whose degree is limited to the one of the polynomial generator of the corresponding CRC code. The calculations include also look up operations in tables limited in size. The choice between the possible implementations (full software, full hardware and mixed hardware and software with the usage of a Remult operator for the last two) will depend on the kind of the network (Frame Relay or other network) and the capacity of the intermediate network node.
摘要翻译：的方法和设备，以在通信网络的中间节点计算，追加到已在所述中间网络节点被修改一个数据比特消息的新的帧校验序列（FCS）。本发明是用于高速网络，其中所述传送延迟需要将网络地连同在中间网络节点的计算资源在计算机周期和内存大小方面进行优化是有用的。本发明besteht在计算使用该消息中的修改的字段，并在修改后的字段和消息的结束的端部之间的位距离之间的差的FCS之间的差; 在数据流并且提供到优化处理的短消息区分“短消息”的计算besteht，对于较大的消息的处理是基于该第一优化处理。修改后的FCS包括操作对多项式的系数属于伽罗瓦的场和谁程度仅限于相应的CRC码的生成多项式的一个计算。因此，计算包括在大小限制表查找操作。在可能的实施方式之间的选择（全软件，全硬件和混合的硬件和软件具有用于Remult操作者的使用负载2）将取决于种类网络（帧中继或其它网络）的和中间的容量网络节点。

89. 发明公开

EP0313707A1 Data integrity securing means 失效
标题翻译： MittelfürDatenintegritätssicherung。
公开(公告)号：EP0313707A1
公开(公告)日：1989-05-03
申请号：EP87480017.0
申请日：1987-10-30
申请人： International Business Machines Corporation
发明人： Calvignac, Jean , Dauphin, Michel , Lenoir, Raymond , Picard, Jean-Louis
IPC分类号： H04L1/00 , H03M13/00
CPC分类号： H03M13/093 , H04L1/0083
摘要： A process for updating the frame check sequence FCS r (x) of a digital frame including an embedded variable header polynomial H r (x), said process including : XORing the modified polynomial header H t (x) and previous polynomial header H r (x) to generate a differential polynomial D(x); computing a differential frame check polynomial sequence dFCS (x) on said D(x) and adding dFCS(x) to the polynomial FCS r (x).
摘要翻译：一种用于更新包括嵌入式可变标题多项式Hr（x）的数字帧的帧校验序列FCSr（x）的处理，所述处理包括：将修改的多项式标题Ht（x）和先前的多项式标题Hr（x）进行异或以产生微分多项式D（x）; 在所述D（x）上计算差分帧校验多项式序列dFCS（x），并将dFCS（x）加到多项式FCSr（x）。

90. 发明公开

KR1020090026238A 비검출 오류 저감을 위한 신호 분할 및 ＣＲＣ 부착 방법 有权
标题翻译：用于减少未受保护的错误的信号分割方法和CRC连接方法
公开(公告)号：KR1020090026238A
公开(公告)日：2009-03-12
申请号：KR1020070123438
申请日：2007-11-30
申请人： 엘지전자 주식회사
发明人： 서동연 , 김봉회 , 윤영우 , 이대원 , 유남열 , 김기준 , 노동욱
IPC分类号： H04L1/24 , H04L1/22
CPC分类号： H04L1/0061 , G06F11/1004 , H03M13/09 , H03M13/093 , H04L1/0041 , H04L1/0042 , H04L1/0078
摘要： A signal segmentation method and a CRC(Cyclic Redundancy Check) attachment method are provided to reduce an undetected error probability in attaching a CRC to a signal block of short length and a signal block of long length. A first CRC is attached in a first signal block of a first length(S301), and is generated by a first type CRC generating polynomial equation. The first signal block of the first length is divided into a plurality of second signal block of a second length(S302). The second length is shorter than the first length. A second CRC is attached in the second signal block(S303), and is generated by a second type CRC generating polynomial equation. The first signal block of the first length is a transport block. The second signal block of the second length is a code block. The first CRC and the second CRC have length of 24 bit.
摘要翻译：提供信号分割方法和CRC（循环冗余校验）连接方法，以减少将CRC附加到长度长的信号块和长度长的信号块上的未检测到的错误概率。第一CRC附加在第一长度的第一信号块（S301）中，并且由第一类型CRC生成多项式方程生成。第一长度的第一信号块被划分成多个第二长度的第二信号块（S302）。第二长度比第一长度短。第二个CRC附加在第二信号块（S303）中，并由第二类型的CRC生成多项式方程式产生。第一长度的第一信号块是传输块。第二长度的第二信号块是码块。第一个CRC和第二个CRC的长度为24位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式