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81. 发明授权

EP1363399B1 Clock and data recovery circuit and clock control method thereof 有权
标题翻译：数据和时钟恢复和相应的时钟控制程序电路装置
公开(公告)号：EP1363399B1
公开(公告)日：2011-03-23
申请号：EP03010522.5
申请日：2003-05-09
申请人： Renesas Electronics Corporation
发明人： Saeki, Takanori, c/o NEC Electronics Corporation
IPC分类号： H03K5/00
CPC分类号： H03L7/091 , H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03K2005/00195 , H03L7/0814 , H03L7/087 , H03L7/0998 , H04L7/0025 , H04L7/0337

82. 发明公开

EP1363399A3 Clock and data recovery circuit and clock control method thereof 有权
标题翻译：数据和时钟恢复和相应的时钟控制程序电路装置
公开(公告)号：EP1363399A3
公开(公告)日：2010-03-31
申请号：EP03010522.5
申请日：2003-05-09
申请人： NEC Electronics Corporation
发明人： Saeki, Takanori, c/o NEC Electronics Corporation
IPC分类号： H03K5/00
CPC分类号： H03L7/091 , H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03K2005/00195 , H03L7/0814 , H03L7/087 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： A clock and data recovery circuit for improving resistance to jitter includes a phase-shift circuit having a switch, to which multiphase clocks are input, for selecting and outputting a plurality of pairs of clocks from among the multiphase clocks, and a plurality of interpolators, to which the plurality of clock pairs output from the switch are input, for outputting clock signals in which delay time is stipulated by time obtained by internally dividing the phase difference between the clocks of the pair; a plurality of latch circuits to which input data is applied in common; a phase detecting circuit for detecting and outputting phase, with respect to the clock, of a transition point of the input data from the outputs of the plurality of latch circuits; a filter for smoothing the output of the phase detecting circuit; and a control circuit for controlling clock phase by outputting control signals for controlling the interpolators and/or switch of the phase-shift circuit based upon the filter output. The plurality of interpolators are divided into a plurality of groups in relation to the control signals supplied from the control circuit, interpolators in the same group are supplied with the same control signal from the control circuit, and interpolators in different groups are supplied separately with the control signals from the control circuit.

83. 发明授权

EP1158678B1 Timing difference division circuit and signal controlling method and apparatus 有权
标题翻译：电路装置以及用于时间间隔的内插方法和使用该电路的时钟产生电路
公开(公告)号：EP1158678B1
公开(公告)日：2006-12-13
申请号：EP01250187.0
申请日：2001-05-26
申请人： NEC Electronics Corporation
发明人： Saeki, Takanori
IPC分类号： H03K5/13 , H03K5/00
CPC分类号： G06F7/68 , H03K5/00006 , H03K5/133 , H03K2005/00065 , H03K2005/00071

84. 发明授权

EP1199800B1 Schaltungsanordnung zur Programmierung einer Verzögerungszeit eines Signalpfads 有权
标题翻译：电路用于编程信号路径的延迟时间
公开(公告)号：EP1199800B1
公开(公告)日：2003-10-29
申请号：EP01120438.5
申请日：2001-08-27
申请人： Infineon Technologies AG
发明人： Dietrich, Stefan, Dr. , Hein, Thomas , Heyne, Patrick , Markert, Michael , Marx, Thilo , Partsch, Torsten , Schöniger, Sabine , Schrögmeier, Peter , Sommer, Michael , Weis, Christian
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03K2005/00091

85. 发明公开

EP1293890A2 Clock control method, frequency dividing circuit and PLL circuit 审中-公开
标题翻译： Taktsteuerungsverfahren，Frequenzteilerschaltung und Phasenregelkreisschaltung
公开(公告)号：EP1293890A2
公开(公告)日：2003-03-19
申请号：EP02019919.6
申请日：2002-09-04
申请人： NEC CORPORATION
发明人： Saeki, Takanori
IPC分类号： G06F7/68
CPC分类号： H03L7/1976 , G06F7/68 , H03K2005/00065 , H03K2005/00071 , H03L7/081 , H03L7/0891 , H03L7/1974
摘要： A PLL circuit includes phase comparator (103) having a first input terminal to which a reference clock is applied; charge pump (104) generating a voltage conforming to a phase difference output from the phase comparator; loop filter (105); VCO (106); frequency dividing circuit (107), to which an output clock of the VCO is input, performing frequency-division by P; A counter (109) dividing the output of the frequency dividing circuit by a second value A; circuits (121,122) generating two signals, which have a phase difference equivalent to one period of the P-frequency-divided output of the frequency dividing circuit, whenever frequency-division by A is performed by the A counter; and interpolator (123), to which the two generated signals are input, producing an output signal of a phase obtained by interpolating the phase difference between the two signals in accordance with an interior division ratio set by a control signal.
摘要翻译： PLL电路包括相位比较器（103），其具有施加了参考时钟的第一输入端; 电荷泵（104）产生符合从相位比较器输出的相位差的电压; 环路滤波器（105）; VCO（106）; 分频电路（107），输入VCO的输出时钟，进行P分频; 将分频电路的输出除以第二值A的计数器（109）电路（121,122）产生两个信号，每当由A计数器执行A分频时，其具有相当于分频电路的P分频输出的一个周期的相位差; 和输入了两个生成信号的内插器（123），根据由控制信号设定的内部分频比，产生通过内插两个信号之间的相位差而获得的相位的输出信号。

86. 发明公开

EP1260822A2 Automatic test equipment for semiconductor device 失效
标题翻译：自动电路测试器用于半导体器件
公开(公告)号：EP1260822A2
公开(公告)日：2002-11-27
申请号：EP02013298.1
申请日：1998-07-22
申请人： TERADYNE, INC.
发明人： Sartschev, Ronald A. , Meuthing, Gerald F., Jr.
IPC分类号： G01R31/319
CPC分类号： H03L7/0805 , G01R31/3191 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00026 , H03K2005/00065 , H03K2005/00071 , H03K2005/00195 , H03K2005/00208 , H03L7/0812
摘要： Automatic lest equipment for testing semiconductor devices equipment includes

a) a clock;
b) a delay line comprised of a plurality of delay stages (212), each delay stage (212) having an input and an output and a control input, with the input of the first delay stage (212(0)) coupled to the clock and the input of every other delay stage coupled to the output of the preceding stage in the delay line; said automatic test equipment characterised by:
c) a phase detector (214) having a first input coupled to an output of a delay stage in the delay line and in an input coupled to the output of a prior delay stage in the delay line; and
d) a control circuit (216) having an input coupled to the output of the phase detector and an output connected to the control inputs of each of the delay stages in the delay line.

87. 发明公开

EP1178610A3 Delay circuit for ring oscillator with power supply noise compensation 有权
标题翻译：延迟电路，用于与电源噪声的补偿环形振荡器
公开(公告)号：EP1178610A3
公开(公告)日：2002-04-10
申请号：EP01402082.0
申请日：2001-08-01
申请人： SONY CORPORATION
发明人： Tachimori, Hiroshi, c/o Sony LSI Design Corp
IPC分类号： H03L7/099 , H03K3/011 , H03K3/0231
CPC分类号： H03K3/013 , H03K3/0315 , H03K5/133 , H03K2005/00039 , H03K2005/00065 , H03K2005/00071 , H03K2005/00195 , H03K2005/00202 , H03L7/0812 , H03L7/0893 , H03L7/0995
摘要： An inverter type delay circuit, voltage-controlled oscillation circuit, and voltage-controlled delay circuit capable of realizing simplification of circuit configuration, reduction of an effect of power source noise, and reduction of jitter, wherein a delay circuit (100), voltage-controlled oscillation circuit, and voltage-controlled delay circuit comprised of a plurality of delay stages controlled in drive current in accordance with a bias voltage or a control voltage (Vcnt1, ..., Vcntj) and determined in delay time by the drive current, adding a change (ΔVdd) of a power source voltage (Vdd) to the above bias voltage or control voltage (Vcnt1, ..., Vcntj) by a predetermined ratio (kc1, ..., kcj) and supplying a result of the addition (Vc1, ... Vcj) to the above delay stages to suppress the power source voltage dependencies of the delay times of the delay stages, or connecting by a predetermined ratio a plurality of delay stages having different power source voltage dependencies, for example, power source voltage dependencies of opposite delay times, to suppress the power source voltage dependencies of delay times of the delay stages are realized.

88. 发明公开

EP1000364A1 LOW COST CMOS TESTER WITH HIGH CHANNEL DENSITY 失效
标题翻译：具有高通道密度低成本CMOS测试仪
公开(公告)号：EP1000364A1
公开(公告)日：2000-05-17
申请号：EP98935953.4
申请日：1998-07-22
申请人： TERADYNE, INC.
发明人： SARTSCHEV, Ronald, A. , MUETHING, Gerald, F., Jr.
IPC分类号： G01R31/319 , H03K5/13
CPC分类号： H03L7/0805 , G01R31/3191 , G01R31/31922 , H03K5/131 , H03K5/133 , H03K2005/00026 , H03K2005/00065 , H03K2005/00071 , H03K2005/00195 , H03K2005/00208 , H03L7/0812
摘要： Automatic test equipment for testing semiconductor devices equipment includes a) a clock; b) a delay line comprised of a plurality of delay stages (212), each delay stage (212) having an input and an output and a control input, with the input of the first delay stage (212(0)) coupled to the clock and the input of every other delay stage coupled to the output of the preceding stage in the delay line; said automatic test equipment characterised by: c) a phase detector (214) having a first input coupled to an output of a delay stage in the delay line and in an input coupled to the output of a prior delay stage in the delay line; and d) a control circuit (216) having an input coupled to the output of the phase detector and an output connected to the control inputs of each of the delay stages in the delay line.

89. 发明公开

EP0424222A1 Circuit intégré logique, à temps de basculement réglable 失效
标题翻译： Integrierte Logikschaltung mit einstellbarenÜbergangszeiten。
公开(公告)号：EP0424222A1
公开(公告)日：1991-04-24
申请号：EP90402855.2
申请日：1990-10-12
申请人： THOMSON COMPOSANTS MICROONDES
发明人： Gobbi, José Maria , Le Berre, Louis
IPC分类号： H03K19/0952 , H01L27/02
CPC分类号： H01L27/11803 , H03K5/133 , H03K19/00323 , H03K19/0952 , H03K2005/00065 , H03K2005/00195
摘要： L'invention concerne un circuit intégré logique dont le temps de basculement entre deux états logiques 0 et 1 est réglable.
Dans une porte logique telle qu'un inverseur (7+8), le temps de basculement, sur la sortie (S), est fonction du courant débité par le transistor de charge (8) ou par le transistor de signal (7). Ce temps est réglable, soit en temps de montée, soit en temps de descente , en remplaçant au moins un transistor monodrain par un transistor multidrains (7), dont le débit est fixé par le nombre de drains connectés.
Application aux circuits prédiffusés (Si) ou préimplantés (GaAs).
摘要翻译：本发明涉及一种可在两个逻辑状态0和1之间转换的时间可调的逻辑集成电路。在诸如反相器（7 + 8）的逻辑门中，输出（S）上的转变时间是由负载晶体管（8）或信号晶体管（8）吸收的电流的函数， 7）。这个时间可以在上升时间或在下降时间内通过用多连接晶体管（7）代替至少一个单漏极晶体管，其吞吐量由连接的漏极的数量来确定。 ...适用于半定制（Si）或预插入（GaAs）电路。 ... ...

90. 发明公开

EP0423963A2 Temperature self-compensated time delay circuits 失效
标题翻译： Temitaturkompensation（Zeitverzögerungsschaltungen）
公开(公告)号：EP0423963A2
公开(公告)日：1991-04-24
申请号：EP90310649.0
申请日：1990-09-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Chen, Kou-Su
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00143 , H03K2005/00195
摘要： A constant time delay circuit which is insensitive to variations in temperature and has no D.C. power dissipation includes a temperature-insensitive reference current source (12) for dynamically charging and discharging a capacitive load (M5), a polysilicon resistor (16), and at least one time delay control circuit (14) to produce a constant time delay. In an alternate embodiment, there is provided a temperature self-compensated programmable delay circuit which includes electrically programmable resistor means (30) for adjusting the total resistance in a temperature-insensitive reference current source (12b). As a result, the amount of the reference current is controlled so as to obtain a desired delay time.
摘要翻译：对温度变化不敏感并且没有直流功率耗散的恒定时间延迟电路包括用于动态地对容性负载（M5）充电和放电的温度不敏感参考电流源（12），多晶硅电阻器（16）至少一个时间延迟控制电路（14）产生恒定的时间延迟。在替代实施例中，提供了一种温度自补偿可编程延迟电路，其包括用于调节温度不敏感参考电流源（12b）中的总电阻的电可编程电阻器装置（30）。结果，控制参考电流的量以获得期望的延迟时间。

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