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    • 86. 发明公开
    • Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein
    • 一种频率合成器,用于产生高纯度的信号以及相关联的电路元件,例如VCO,PLL和信号发生器的发电机。
    • EP0414260A2
    • 1991-02-27
    • EP90116261.0
    • 1990-08-24
    • ANRITSU CORPORATION
    • Saeki Anritsu Okihara-Ryou, HiroshiMotoyama, Hatsuo
    • H03B21/01H03L7/087H03L7/099H03B19/16
    • H03B19/16H03B5/1203H03B5/1231H03B5/1243H03B5/1262H03B5/1293H03B19/20H03B21/01H03B2200/0034H03B2200/0042H03B2201/0208H03B2201/0216H03B2201/033H03L7/093H03L7/113
    • To output desired high purity signals, a frequency synthesizer was made to synthesize reference signals from a first and second signal generators (11, 12) in the same frequency band as a desired frequency band. Thereby, the resolution of the frequency synthesizer becomes twice the step ΔF. Also, the frequency synthe­sizer can interpolate the step size of the first signal generator with half the number of steps. While, heretofore, the 100-MHz step size was interpolated with Fq = 0, 10, 20, 30, 40 and 50 MHz, Fq = 0, 20, 40 MHz interpolation is made possible. This permits the syn­thesis of 580 MHz to 1280 MHz. In this case, however, the minimum difference between the sum and difference frequencies from the first and second signal generators (11, 12) is 40 MHz and the lowest frequency is 20 MHz. Thus, depending on mixer isolation, the spurious meas­ures become difficult. The frequency synthesizer of the present invention pays attention to the fact that 20 MHz step signals can be synthesized at frequencies which are integral multiples of Fq (multiples of 0 and 5 are excluded). When two-fold Fq is used, the minimum dif­ference between the sum and difference frequencies out­put from a mixer (13) is 80 MHz and the lowest used frequency is 40 MHz. The spurious measures by a PLL circuit (14) becomes easy. A frequency detector (18) forces the free-running frequency of a VCO included the PLL circuit. Control Data P and Q to the first and sec­ond signal generators are supplied from a control sec­tion (27) based on data Fi set by as frequency setting section (28).
    • 为了输出所需的高纯度的信号,这使得从在相同的频带作为一种期望的频率带的第一和第二信号发生器(11,12)合成的参考信号的频率合成器。 由此,频率合成器的分辨率变为两倍的步骤DELTA F.因此,频率合成器可以与步骤一半数量的内插所述第一信号发生器的步长大小。 而,迄今为止,在100-MHz的步长大小,其与Fq中= 0,10,20,30,40和50兆赫,F Q = 0,20,40 MHz的内插是可能的内插。 这允许580兆赫的合成,1280兆赫。 在这种情况下,然而,和与差之间的最小差值从所述第一和第二信号发生器频率(11,12)为40MHz,而最低频率为20MHz。 因此,根据混频器的隔离,寄生措施变得困难。 本发明的频率合成器注重可以在哪些是Fq上的整数倍的频率进行合成的factthat 20MHz的步骤信号(0和5的倍数除外)。 当使用两倍FQ,和与差之间的最小差值频率从混频器输出(13)是80MHz,最低使用频率为40兆赫。 由PLL电路(14)的寄生措施变得容易。 频率检测器(18)强制VCO的自由运行频率包括在PLL电路。 控制数据P和Q,以将第一和第二信号发生器,从一个控制部分(27),基于由设定为频率设定部(28)的数据网络连接提供。
    • 87. 发明公开
    • Transistor circuit including biasing circuit
    • Transistorschaltung mit Vorspannungskreis。
    • EP0080209A1
    • 1983-06-01
    • EP82110841.2
    • 1982-11-23
    • NEC CORPORATION
    • Sasaki, Yutaka
    • H03F1/30H03B5/04
    • H03F3/19H03B5/04H03B5/1805H03B5/1847H03B2200/0008H03B2200/0034H03B2200/004H03B2200/0062H03B2200/0082H03B2201/0208H03F1/302
    • There is provided a transistor circuit for amplification or oscillation capable of reducing power consumption in voltage dividing resistors for biassing use and of suppressing the variation of its characteristic owing to temperature change. The transistor circuit has a first transistor means (113) for amplification or oscillation and a biassing means for supplying a D.C. biassing voltage to the base of the first transistor means. The biassing means comprises a voltage dividing resistor means (111, 112) having an output terminal for providing a divided D.C. voltage, and a second transistor means (115) constituting an emitter follower circuit means, whose base is connected to the output terminal and whose emitter is coupled to the base of the first transistor means to provide the D.C. biassing voltage. Furthermore, the first transistor means may have an inverse conductive junction structure to that of the second transistor means.
    • 提供了用于放大或振荡的晶体管电路,其能够降低用于偏压使用的分压电阻器中的功耗,并且由于温度变化而抑制其特性的变化。 晶体管电路具有用于放大或振荡的第一晶体管装置(113)和用于向第一晶体管装置的基极提供直流偏置电压的偏置装置。 偏置装置包括具有用于提供分压直流电压的输出端子的分压电阻器件(111,112),以及构成射极跟随器电路装置的第二晶体管装置(115),其基极连接到输出端子, 发射极耦合到第一晶体管装置的基极以提供直流偏置电压。 此外,第一晶体管装置可具有与第二晶体管装置相反的导电结结构。