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81. 发明申请

US20160181220A1 Dummy Flip Chip Bumps for Reducing Stress 审中-公开
公开(公告)号：US20160181220A1
公开(公告)日：2016-06-23
申请号：US15054357
申请日：2016-02-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Sheng-Yu Wu , Tin-Hao Kuo , Chita Chuang , Chen-Shien Chen
IPC分类号： H01L23/00 , H01L21/56
CPC分类号： H01L24/17 , H01L21/563 , H01L23/3171 , H01L23/522 , H01L23/53238 , H01L23/562 , H01L23/585 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2021/60255 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05541 , H01L2224/05569 , H01L2224/05572 , H01L2224/05582 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05671 , H01L2224/05684 , H01L2224/06102 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/13022 , H01L2224/13024 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1403 , H01L2224/14051 , H01L2224/141 , H01L2224/14152 , H01L2224/14179 , H01L2224/16237 , H01L2224/16238 , H01L2224/17104 , H01L2224/17517 , H01L2224/73204 , H01L2224/81007 , H01L2224/81101 , H01L2224/81191 , H01L2224/81815 , H01L2224/83104 , H01L2924/01029 , H01L2924/01047 , H01L2924/04941 , H01L2924/04953 , H01L2924/15787 , H01L2924/15788 , H01L2924/35 , H01L2924/3511 , H01L2924/00014 , H01L2924/014 , H01L2924/206 , H01L2924/00
摘要： A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.

82. 发明授权

US09307641B2 Wiring substrate and semiconductor device 有权
标题翻译：接线基板和半导体器件
公开(公告)号：US09307641B2
公开(公告)日：2016-04-05
申请号：US14633525
申请日：2015-02-27
申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.
发明人： Kiyoshi Oi , Takashi Kurihara
IPC分类号： H01L23/12 , H05K1/11 , H01L23/498 , H01L23/00 , H01L25/065 , H05K1/02
CPC分类号： H05K1/111 , H01L21/4857 , H01L23/49811 , H01L23/49822 , H01L23/5385 , H01L23/5389 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/0655 , H01L25/105 , H01L2224/0401 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/17104 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2924/12042 , H01L2924/1432 , H01L2924/1434 , H01L2924/1533 , H01L2924/181 , H05K1/0298 , H05K1/112 , H05K1/113 , H05K3/4007 , H05K3/4644 , H01L2924/00
摘要： A wiring substrate includes a first multi-layer wiring layer including an insulating layer formed of a non-photosensitive resin, a plurality of external connection pads formed on an upper face side of the first multi-layer wiring layer, and a second multi-layer wiring layer formed on the first multi-layer wiring layer, the second multi-layer wiring layer including an insulating layer formed of a photosensitive resin, the second multi-layer wiring layer having a wiring pitch narrower than the wiring pitch of the first multi-layer wiring layer. The external connection pads are exposed from the insulating layer of the second multi-layer wiring layer.
摘要翻译：布线基板包括：第一多层布线层，包括由非感光性树脂形成的绝缘层，形成在第一多层布线层的上表面侧的多个外部连接焊盘，以及第二多层布线层所述第二多层布线层包括由感光性树脂形成的绝缘层，所述第二多层布线层的布线间距比所述第一多层布线层的布线间距窄，层布线层。外部连接焊盘从第二多层布线层的绝缘层露出。

83. 发明授权

US09263376B2 Chip interposer, semiconductor device, and method for manufacturing a semiconductor device 有权
标题翻译：芯片插入器，半导体器件和半导体器件的制造方法
公开(公告)号：US09263376B2
公开(公告)日：2016-02-16
申请号：US13862524
申请日：2013-04-15
申请人： Intel Mobile Communications GmbH
发明人： Thorsten Meyer , Gerald Ofner
IPC分类号： H01L23/48 , H01L23/498 , H01L23/00
CPC分类号： H01L23/498 , H01L23/13 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/81 , H01L2224/0345 , H01L2224/0401 , H01L2224/05166 , H01L2224/05171 , H01L2224/05567 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/10175 , H01L2224/1132 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11474 , H01L2224/11849 , H01L2224/11903 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13171 , H01L2224/13184 , H01L2224/13561 , H01L2224/136 , H01L2224/1403 , H01L2224/141 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/171 , H01L2224/17104 , H01L2224/81193 , H01L2224/81203 , H01L2224/81385 , H01L2224/814 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81466 , H01L2224/81471 , H01L2224/81484 , H01L2224/81801 , H01L2924/12042 , H01L2924/1461 , H01L2924/381 , H01L2924/3841 , H01L2924/00 , H01L2924/014 , H01L2924/00015 , H01L2924/00014 , H01L2924/01074 , H01L2924/00012 , H01L2924/01013
摘要： A chip interposer may include: a first interconnect level including a first pad; and a second interconnect level including a second pad, wherein the second pad may face in the same direction as the first pad.
摘要翻译：芯片插入器可以包括：第一互连级，包括第一焊盘; 以及包括第二焊盘的第二互连级别，其中所述第二焊盘可以面向与所述第一焊盘相同的方向。

84. 发明申请

US20150243620A1 SUBSTRATE AND PACKAGE STRUCTURE 有权
标题翻译：基板和封装结构
公开(公告)号：US20150243620A1
公开(公告)日：2015-08-27
申请号：US14190360
申请日：2014-02-26
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： WEI-HUNG LIN , HSIU-JEN LIN , MING-DA CHENG , YU-MIN LIANG , CHEN-SHIEN CHEN , CHUNG-SHI LIU
IPC分类号： H01L23/00
CPC分类号： H01L24/17 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/13005 , H01L2224/13082 , H01L2224/131 , H01L2224/1403 , H01L2224/16013 , H01L2224/16104 , H01L2224/16238 , H01L2224/1701 , H01L2224/1703 , H01L2224/17104 , H01L2924/014 , H01L2924/00014 , H01L2924/207
摘要： According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
摘要翻译：根据示例性实施例，提供具有第一区域和第二区域的基板。基板包括多个焊盘。每个垫具有垫尺寸。第一区域中的焊盘尺寸大于第二区域中的焊盘尺寸。

85. 发明授权

US08896133B2 Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate 有权
标题翻译：半导体器件和在第一衬底上形成垂直偏移的导电柱的方法，其对准在第二衬底上形成的垂直偏移的BOT互连位置
公开(公告)号：US08896133B2
公开(公告)日：2014-11-25
申请号：US13870928
申请日：2013-04-25
申请人： STATS ChipPAC, Ltd.
发明人： SungWon Cho , KiYoun Jang , YongHee Kang , Hyung Sang Park
IPC分类号： H01L23/48 , H01L21/48 , H01L23/00 , H01L23/498 , H01L21/56
CPC分类号： H01L24/09 , H01L21/4857 , H01L21/563 , H01L23/49822 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/81 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/1155 , H01L2224/11831 , H01L2224/11849 , H01L2224/11901 , H01L2224/11903 , H01L2224/13023 , H01L2224/13082 , H01L2224/13083 , H01L2224/13099 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/141 , H01L2224/16225 , H01L2224/16237 , H01L2224/16238 , H01L2224/17104 , H01L2224/29144 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48158 , H01L2224/73204 , H01L2224/73265 , H01L2224/81011 , H01L2224/81022 , H01L2224/81024 , H01L2224/81193 , H01L2224/81385 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81801 , H01L2224/83102 , H01L2224/8385 , H01L2224/92125 , H01L2924/00014 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/10335 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3841 , H01L2924/01014 , H01L2924/0105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.
摘要翻译：半导体器件具有形成在第一衬底上的第一衬底和第一导电柱。第二导电柱形成在第一基板上，与第一导电柱交替。第二导电柱相对于第一导电柱垂直偏移。第一BOT互连位点形成在第二基底上。第二BOT互连位置形成在第二衬底上与第一互连位置交替。第二互连站点相对于第一互连站点垂直偏移。第一衬底安装到第二衬底，使得第一导电柱与第一互连位置对准并电连接，并且第二导电柱与第二互连位置对准并电连接到第二互连位置。底部填充材料沉积在第一和第二基底之间。第一基板可以是倒装芯片型半导体器件。

86. 发明授权

US08791558B2 Stacked semiconductor package 有权
标题翻译：堆叠半导体封装
公开(公告)号：US08791558B2
公开(公告)日：2014-07-29
申请号：US12980772
申请日：2010-12-29
申请人： Jin Ho Bae , Ki Young Kim , Jong Hyun Nam
发明人： Jin Ho Bae , Ki Young Kim , Jong Hyun Nam
IPC分类号： H01L23/02 , H01L23/48 , H01L23/28 , H01L23/52 , H01L29/40
CPC分类号： H01L24/17 , H01L23/49816 , H01L24/09 , H01L24/16 , H01L24/18 , H01L24/20 , H01L24/29 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/04105 , H01L2224/17104 , H01L2224/18 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73265 , H01L2224/73267 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06586 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate.
摘要翻译：叠层半导体芯片包括支撑半导体芯片模块的主衬底，其中半导体模块包括至少两个次半导体芯片模块，每个子半导体芯片模块具有嵌入第一半导体芯片的子衬底，并且至少两个第二半导体芯片堆叠在副底物。

87. 发明申请

US20140191397A1 PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 审中-公开
标题翻译：封装衬底和半导体封装，包括它们
公开(公告)号：US20140191397A1
公开(公告)日：2014-07-10
申请号：US14206002
申请日：2014-03-12
申请人： Samsung Electronics Co., Ltd.
发明人： Tae-Gyu KANG , Ho-Tae JIN , Tae-ho MOON , Il-Soo CHOI , Jong-Eun LEE
IPC分类号： H01L23/00
CPC分类号： H01L24/14 , H01L23/49816 , H01L23/49838 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/06102 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/14515 , H01L2224/16237 , H01L2224/17104 , H01L2224/17517 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.
摘要翻译：封装基板可以包括绝缘基板，虚拟焊盘，信号焊盘和插头。虚拟焊盘可以形成在绝缘基板的上表面上。信号焊盘可以形成在绝缘基板的上表面上。信号垫可以具有从虚拟垫的上表面突出的上表面。插塞可以垂直地形成在绝缘基板中。插头可以具有通过绝缘基板的上表面暴露的上端，并且与信号焊盘和虚拟焊盘相连，并且通过绝缘基板的下表面露出的下端。因此，信号凸块可以准确地与信号垫的突出的上表面接触。

88. 发明授权

US08664041B2 Method for designing a package and substrate layout 有权
标题翻译：设计封装和基板布局的方法
公开(公告)号：US08664041B2
公开(公告)日：2014-03-04
申请号：US13445699
申请日：2012-04-12
申请人： Yu-Jen Tseng , Guan-Yu Chen , Sheng-Yu Wu , Chen-Hua Yu , Mirng-Ji Lii , Chen-Shien Chen , Tin-Hao Kuo
发明人： Yu-Jen Tseng , Guan-Yu Chen , Sheng-Yu Wu , Chen-Hua Yu , Mirng-Ji Lii , Chen-Shien Chen , Tin-Hao Kuo
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： G06F17/5068 , H01L23/3192 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0401 , H01L2224/05558 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11849 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/17104 , H01L2224/81191 , H01L2224/81385 , H01L2224/81444 , H01L2224/81815 , H01L2924/00014 , H01L2924/014 , H01L2924/00012 , H01L2924/01029 , H01L2924/01074 , H01L2224/1144
摘要： A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.
摘要翻译：一种用于防止在跟踪轨迹结构中的相邻金属迹线桥接的方法和装置。一个实施例包括确定包装部件的热膨胀系数（CTE）和工艺参数。然后分析设计参数，并且可以基于包装部件的CTE和工艺参数来修改设计参数。

89. 发明授权

US07665648B2 Fabrication method and structure of PCB assembly, and tool for assembly thereof 有权
标题翻译： PCB组装的制造方法和结构以及其组装工具
公开(公告)号：US07665648B2
公开(公告)日：2010-02-23
申请号：US11858837
申请日：2007-09-20
申请人： Chun-Chieh Pan
发明人： Chun-Chieh Pan
IPC分类号： B23K31/02
CPC分类号： H01L24/73 , H01L24/14 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/13013 , H01L2224/13014 , H01L2224/13016 , H01L2224/13027 , H01L2224/13099 , H01L2224/13111 , H01L2224/14051 , H01L2224/14104 , H01L2224/16237 , H01L2224/17104 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K2201/09381 , H05K2201/094 , H05K2203/0465 , Y02P70/613 , Y10T29/49144 , H01L2924/00012 , H01L2224/05599
摘要： A fabrication method and structure for a PCBA, and tool for assembly of the structure. The structure includes a circuit board, at least one first solder joint, a plurality of second solder joints, and an electronic device. The circuit board has a solder mask, having a plurality of openings exposing at least one first pad and a plurality of second pads arranged beyond the first pad, on a surface. The first solder joint has a maximum width J1 and electrically connects to the first pad. The second solder joints respectively have a maximum width J2 exceeding J1 and respectively electrically connect to the second pads. The electronic device has a plurality of third pads, arranged substantially corresponding to the openings, respectively electrically connecting to the first pad and second pads.
摘要翻译： PCBA的制造方法和结构，以及用于组装结构的工具。该结构包括电路板，至少一个第一焊接接头，多个第二焊点和电子器件。电路板具有焊接掩模，其具有在表面上暴露至少一个第一焊盘和布置成超过第一焊盘的多个第二焊盘的多个开口。第一焊点具有最大宽度J1并且电连接到第一焊盘。第二焊点分别具有超过J1的最大宽度J2并分别电连接到第二焊盘。电子设备具有多个第三焊盘，其大致对应于开口分别电连接到第一焊盘和第二焊盘。

90. 发明授权

US07436063B2 Packaging substrate and semiconductor device 有权
标题翻译：包装基板和半导体器件
公开(公告)号：US07436063B2
公开(公告)日：2008-10-14
申请号：US11242125
申请日：2005-10-04
申请人： Osamu Miyata , Shingo Higuchi
发明人： Osamu Miyata , Shingo Higuchi
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/49838 , H01L2224/16 , H01L2224/17051 , H01L2224/17104 , H01L2924/01078 , H01L2924/00012
摘要： A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings each formed in continuation with each of the electrode openings in the wiring protective layer for introducing therein a part of the connection metal body to be connected to each of the electrode parts to escape.
摘要翻译：根据本发明的封装基板是其表面上具有多个连接金属体的半导体芯片与与封装基板相对的表面接合的封装基板，并且包括设置在接合表面上的布线，半导体芯片接合，设置在接合表面上并电连接到布线的多个电极部分，用于涂覆和保护布线的布线保护层，通过部分地打开布线保护层而形成的电极开口，用于分别暴露每个电极以及与布线保护层中的每个电极开口连续形成的排出口，用于引入要连接到每个电极部分的连接金属体的一部分以逃逸。

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