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81. 发明申请

US20170154656A1 DATA PROGRAMMING METHOD AND MEMORY STORAGE DEVICE 审中-公开
公开(公告)号：US20170154656A1
公开(公告)日：2017-06-01
申请号：US14997575
申请日：2016-01-18
申请人： PHISON ELECTRONICS CORP.
发明人： Chih-Kang Yeh
IPC分类号： G11C7/00 , G11C29/52 , G06F11/10
CPC分类号： G11C7/00 , G06F3/0679 , G06F11/1068 , G06F12/0246 , G11C5/005 , G11C7/1006 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/345 , G11C29/42 , G11C29/52
摘要： A data programming method and a memory storage device are provided. The method includes: programming a plurality of first type physical units in a rewritable non-volatile memory module to store first data; encoding the first data to generate encoded data; receiving second data; and programming at least one of a plurality of second type physical units in the rewritable non-volatile memory module corresponding to the first type physical units to store at least a part of the second data after the first data is encoded. Therefore, the correcting ability for correcting errors in pair physical units in multi-channel programming procedure may be improved.

82. 发明授权

US09627079B1 Storage device, memory system having the same, and operating method thereof 有权
公开(公告)号：US09627079B1
公开(公告)日：2017-04-18
申请号：US15093935
申请日：2016-04-08
申请人： SK hynix Inc.
发明人： Yong Hwan Hong , Byung Ryul Kim
IPC分类号： G11C11/34 , G11C16/16 , G11C16/08 , G11C16/10
CPC分类号： G11C16/16 , G11C16/08 , G11C16/10 , G11C16/3409 , G11C16/345
摘要： There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory bocks are performed.

83. 发明授权

US09343172B2 Extended protection for embedded erase of non-volatile memory cells 有权
标题翻译：扩展保护非易失性存储单元的嵌入式擦除
公开(公告)号：US09343172B2
公开(公告)日：2016-05-17
申请号：US13965731
申请日：2013-08-13
申请人： Fuchen Mu , Chen He , Yanzhuo Wang
发明人： Fuchen Mu , Chen He , Yanzhuo Wang
IPC分类号： G11C11/34 , G11C16/34 , G11C16/14
CPC分类号： G11C16/3459 , G11C16/14 , G11C16/345
摘要： Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level and lower than read voltage level (VR).
摘要翻译：公开了用于NVM系统的嵌入式擦除操作期间用于非易失性存储器（NVM）单元的扩展擦除保护的方法和系统。本文描述的实施例在嵌入式擦除操作中的软编程操作完成之后利用额外的阈值电压（Vt）检查，以提供NVM单元的扩展擦除保护。特别地，NVM单元的阈值电压与阈值电压（Vt）检查电压（VCHK）电平进行比较，并且如果发现任何NVM单元超过阈值电压（Vt）检查电压（VCHK），执行附加的嵌入式擦除周期）级别。阈值电压（Vt）检查电压（VCHK）电平可以是例如略高于擦除验证电压（VEV）电平且低于读取电压电平（VR）的电压电平。

84. 发明授权

US09070474B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09070474B2
公开(公告)日：2015-06-30
申请号：US14019731
申请日：2013-09-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tatsuo Izumi
IPC分类号： G11C11/34 , G11C16/06 , G11C16/34 , G11C16/16
CPC分类号： G11C16/344 , G11C16/16 , G11C16/3445 , G11C16/345
摘要： An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included in the NAND cell unit, and applies a first read pass voltage to memory cells other than the first group of memory cells. The second erase verify operation is an operation that applies the verify read voltage to a second group of memory cells different from the first group of memory cells, and applies a second read pass voltage different from the first read pass voltage to memory cells other than the second group of memory cells.
摘要翻译：执行擦除验证操作被划分为至少第一擦除验证操作和第二擦除验证操作。第一擦除验证操作是将验证读取电压仅施加到包括在NAND单元单元中的多个存储单元中的第一组存储单元的操作，并将第一读取通过电压施加到除了第一组之外的存储单元的记忆细胞。第二擦除验证操作是将验证读取电压施加到与第一组存储器单元不同的第二组存储器单元的操作，并将不同于第一读取通过电压的第二读取通过电压施加到除第二组记忆细胞。

85. 发明申请

US20130294173A1 METHOD AND APPARATUS FOR THE ERASE SUSPEND OPERATION 有权
标题翻译：擦除操作的方法和装置
公开(公告)号：US20130294173A1
公开(公告)日：2013-11-07
申请号：US13936620
申请日：2013-07-08
申请人： Macronix International Co., Ltd.
发明人： Chuan-Ying Yu , Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/345 , G11C16/3454
摘要： Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
摘要翻译：非易失性存储器的各个方面具有改进的擦除暂停过程。偏移布置被施加到经历由擦除暂停过程中断的擦除过程的擦除扇区的字线。结果，由于擦除扇区的任何被擦除的非易失性存储单元的漏电流减少，因此在诸如读操作或程序操作的擦除暂停期间执行的另一操作具有更精确的结果。

86. 发明授权

US08000147B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08000147B2
公开(公告)日：2011-08-16
申请号：US12781396
申请日：2010-05-17
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的存储单元。对所有存储单元进行擦除操作。然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极记忆细胞因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

87. 发明授权

US08000143B2 Nonvolatile memory device including circuit formed of thin film transistors 有权
标题翻译：包括由薄膜晶体管形成的电路的非易失性存储器件
公开(公告)号：US08000143B2
公开(公告)日：2011-08-16
申请号：US12888974
申请日：2010-09-23
申请人： Taku Ogura , Tadaaki Yamauchi , Takashi Kubo
发明人： Taku Ogura , Tadaaki Yamauchi , Takashi Kubo
IPC分类号： G11C11/34 , G11C29/00 , G11C8/00
CPC分类号： G11C16/344 , G11C7/06 , G11C16/0416 , G11C16/12 , G11C16/345 , G11C16/3477 , G11C2207/005
摘要： A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.
摘要翻译：晶体管被布置为将由薄膜晶体管形成的读出放大器与电耦合到读出放大器的数据线电隔离。当写驱动器驱动数据线时，施加控制信号以将数据线与读出放大器隔离。

88. 发明申请

US20090251965A1 NONVOLATILE MEMORY DEVICE INCLUDING CIRCUIT FORMED OF THIN FILM TRANSISTORS 有权
公开(公告)号：US20090251965A1
公开(公告)日：2009-10-08
申请号：US12483710
申请日：2009-06-12
申请人： Taku OGURA , Tadaaki YAMAUCHI , Takashi KUBO
发明人： Taku OGURA , Tadaaki YAMAUCHI , Takashi KUBO
IPC分类号： G11C16/04 , G11C5/14
CPC分类号： G11C16/344 , G11C7/06 , G11C16/0416 , G11C16/12 , G11C16/345 , G11C16/3477 , G11C2207/005
摘要： A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.

89. 发明申请

US20070189070A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070189070A1
公开(公告)日：2007-08-16
申请号：US11737154
申请日：2007-04-19
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的存储单元。对所有存储单元进行擦除操作。然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极记忆细胞因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

90. 发明申请

US20070140015A1 Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070140015A1
公开(公告)日：2007-06-21
申请号：US11639807
申请日：2006-12-16
申请人： Shoichi Kawamura
发明人： Shoichi Kawamura
IPC分类号： G11C11/34
CPC分类号： G11C16/344 , G11C16/3409 , G11C16/3445 , G11C16/345
摘要： A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device includes a memory cell formed in a first well outputs a first voltage in response to a reference voltage necessary for program and erase verify operations. A reference cell formed in a second well generates a second voltage in response to the reference voltage in the program and erase verify operations. A comparator circuit compares the first voltage to the second voltage to detect whether the verify operation for the memory cell has passed, in the verify operation. A bias applying unit applies the same bias voltage to the first and second wells in the verify operation: Although there is an over-erased cell, an erase verify, operation can be correctly performed.
摘要翻译：非易失性半导体存储器件。非易失性半导体存储器件包括形成在第一阱中的存储单元响应于编程和擦除验证操作所需的参考电压而输出第一电压。形成在第二阱中的参考单元响应于程序中的参考电压和擦除验证操作而产生第二电压。在验证操作中，比较器电路将第一电压与第二电压进行比较，以检测存储单元的验证操作是否已经过去。偏置施加单元在验证操作中向第一和第二阱施加相同的偏置电压：尽管存在过擦除的单元，但可以正确地执行擦除验证操作。

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