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81. 发明申请

US20150067199A1 INTERMITTENT SAMPLING OF STORAGE ACCESS FREQUENCY 有权
标题翻译：存储访问频率的间接采样
公开(公告)号：US20150067199A1
公开(公告)日：2015-03-05
申请号：US14303476
申请日：2014-06-12
申请人： International Business Machines Corporation
发明人： Kevin L. BECK , Kevin J. CHERKAUER
IPC分类号： G06F3/06 , G06F17/30
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0611 , G06F3/0613 , G06F3/0668 , G06F3/0671 , G06F3/0683 , G06F17/30306
摘要： The intermittent sampling of storage access frequency is performed by determining a duration of a collection window and a duration of an observation window within the collection window. A position of the observation window within the collection window is randomly selected, and frequencies of accesses of one or more storage objects during the observation window are observed. When a new access of a given storage object occurs, a delta time for the given storage object is calculated as the time of the observed access minus the timestamp of the most recent observed prior access of the given storage object. Optionally, the delta time of two sequential accesses of a given storage object in two different observation windows may be calculated as if the two different observation windows are immediately adjacent to each other.
摘要翻译：存储访问频率的间歇采样通过确定收集窗口的持续时间和收集窗口内的观察窗口的持续时间来执行。随机选择收集窗口内的观察窗口的位置，观察观察窗口期间一个或多个存储对象的访问频率。当发生给定存储对象的新访问时，给定存储对象的增量时间被计算为观察到的访问的时间减去给定存储对象的最近观察到的先前访问的时间戳。可选地，可以计算两个不同观察窗口中的给定存储对象的两次连续访问的增量时间，就好像两个不同的观察窗口彼此紧邻。

82. 发明申请

US20140059280A1 HOST DEVICE AND SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：主机装置和系统包括它们
公开(公告)号：US20140059280A1
公开(公告)日：2014-02-27
申请号：US14011162
申请日：2013-08-27
申请人： Samsung Electronics Co., Ltd
发明人： Jeon-teak IM , Tae-gyun KIM , Jae-young CHOI
IPC分类号： G06F12/00
CPC分类号： G06F3/0688 , G06F3/061 , G06F3/0629 , G06F3/0656 , G06F3/0668 , G06F12/00 , G06F13/16 , G06F13/1668 , G06F13/1673 , G06F13/385
摘要： A memory module includes a first storage module including a first module controller and a first memory unit. The first storage module is configured to receive first partial data from a host and write the first partial data to the first memory unit. A second storage module includes a second module controller and a second memory unit. The second storage module is configured to receive second partial data from the host and write the second partial data to the second memory unit. The first storage module and the second storage module are configured to connect to the host through a single host interface bus.
摘要翻译：存储器模块包括第一存储模块，其包括第一模块控制器和第一存储器单元。第一存储模块被配置为从主机接收第一部分数据，并将第一部分数据写入第一存储器单元。第二存储模块包括第二模块控制器和第二存储器单元。第二存储模块被配置为从主机接收第二部分数据，并将第二部分数据写入第二存储器单元。第一存储模块和第二存储模块被配置为通过单个主机接口总线连接到主机。

83. 发明申请

US20140047195A1 TRANSACTION CHECK INSTRUCTION FOR MEMORY TRANSACTIONS 有权
标题翻译：交易检查内存交易指示
公开(公告)号：US20140047195A1
公开(公告)日：2014-02-13
申请号：US13657012
申请日：2012-10-22
申请人： INTERNATIONAL BUSINESS MACHINES CORP
发明人： Bradly G. FREY , Guy L. GUTHRIE , Cathy MAY , Derek E. WILLIAMS
IPC分类号： G06F12/00
CPC分类号： G06F3/0668 , G06F9/467 , G06F12/0811
摘要： A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction.
摘要翻译：具有共享存储器系统的数据处理系统的处理单元执行包括事务存储指令的存储器事务处理，该指令使得数据处理系统的处理单元对共享存储器系统的目标存储器块进行条件更新承诺内存交易。存储器事务还包括事务检查指令。响应于执行交易检查指令，处理单元在结束存储器事务之前确定在由事务存储指令的执行引起的条件更新之后是否修改了共享存储器系统的目标存储器块。响应于确定目标存储器块已被修改，处理单元内的条件寄存器被设置为指示存储器事务的冲突。

84. 发明申请

US20120054459A1 REORGANIZATION OF A FRAGMENTED DIRECTORY OF A STORAGE DATA STRUCTURE COMPRISED OF THE FRAGMENTED DIRECTORY AND MEMBERS 有权
标题翻译：存储数据结构被划分的目录和成员所包含的被破译的目录重新组织
公开(公告)号：US20120054459A1
公开(公告)日：2012-03-01
申请号：US12868568
申请日：2010-08-25
申请人： Jon Christopher Belisle , David Charles Reed , Max Douglas Smith
发明人： Jon Christopher Belisle , David Charles Reed , Max Douglas Smith
IPC分类号： G06F12/02
CPC分类号： G06F3/061 , G06F3/0643 , G06F3/0644 , G06F3/0668 , G06F12/023 , G06F2206/1004
摘要： A directory and members are allocated to store a data set, wherein the directory stores pointers to the members to allow data stored in the members to be accessed. The directory is expanded to accommodate an expansion of the data set, causing the directory to be stored in non-contiguous pages and becoming fragmented. A computational device determines that a threshold that measures a level of fragmentation of the directory relative to an amount of storage allocated for the data set has been exceeded. The computational device reorganizes the fragmented directory, into a reorganized directory that is stored in contiguous pages at the end of the data set, in response to determining that the threshold has been exceeded.
摘要翻译：分配目录和成员以存储数据集，其中目录存储指向成员的指针以允许访问存储在成员中的数据。该目录被扩展以适应数据集的扩展，导致目录被存储在不连续的页面中并变得分散。计算设备确定已经超过了测量目录相对于为数据集分配的存储量的碎片级别的阈值。响应于确定已经超过阈值，计算设备将分段目录重新组织成存储在数据集末尾的连续页面中的重新组织的目录。

85. 发明公开

KR20180044773A 정보 수신 장치 및 이를 포함하는 반도체 장치 审中-公开
公开(公告)号：KR20180044773A
公开(公告)日：2018-05-03
申请号：KR20160138713
申请日：2016-10-24
IPC分类号： G06F13/16
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0668 , G11C7/109 , G11C8/12 , G11C8/18 , H03K19/00384
摘要： 본발명은칩 선택신호에따라정보를입력받을수 있는정보수신장치및 이를포함하는반도체장치를제공한다. 본발명의정보수신장치는칩 선택신호와미리설정된칩 아이디신호를비교하는비교부; 및상기비교부의비교결과에기초하여, 입력정보(information)를수신하는버퍼를활성화하기위한버퍼인에이블신호를생성하는버퍼인에이블신호생성부를포함한다.

86. 发明公开

KR1020160124675A 저장장치 적층시스템 有权
标题翻译：存储设备堆栈系统
公开(公告)号：KR1020160124675A
公开(公告)日：2016-10-28
申请号：KR1020160045868
申请日：2016-04-15
申请人： 왈톤 어드밴스드 엔지니어링 인크.
发明人： 홍-치,유 , 마오-팅,장
IPC分类号： G06F3/06
CPC分类号： G06F1/266 , G06F3/0604 , G06F3/0629 , G06F3/0683 , G06F3/06 , G06F3/0601 , G06F3/0668
摘要： 본발명은메인저장장치및 보조저장장치를포함하여구성되는것으로, 상기메인저장장치의전력입력인터페이스및 데이터링크인터페이스로각각전력을얻고외부네트워크에접속하여상기메인저장장치내부에관련전자부품을전지적으로연결시키고, 다시전력출력인터페이스를통해상기보조저장장치의전력수신인터페이스와전기적으로연결됨에따라상기보조저장장치가전력을얻을수 있도록하며, 메인데이터브리지인터페이스는상기보조저장장치의보조데이터브리지인터페이스와전기적으로연결됨에따라전력이인가된후의보조저장모듈과상기보조데이터브리지인터페이스를거쳐상기메인저장장치간에는데이터전송이이루어지는저장장치적층시스템을개시한다.
摘要翻译：存储装置堆叠系统包括主存储装置和辅助存储装置：主存储装置依赖于电源输入接口和数据链路接口，以访问电源和外部网络，并允许内部电子部件电激活; 当辅助存储装置上的电力输出接口和电力接收接口彼此电连接时，辅助存储装置被激活; 当辅助存储设备上的主数据桥接接口和辅助数据桥接接口彼此电连接时，数据可以通过辅助数据桥接接口从主存储设备传输到激活的辅助存储模块。

87. 发明授权

US12130704B2 Encoding and encrypting data in a storage network 有权
公开(公告)号：US12130704B2
公开(公告)日：2024-10-29
申请号：US18479236
申请日：2023-10-02
申请人： Pure Storage, Inc.
发明人： Scott M. Horan , Wesley B. Leggette , Jason K. Resch
IPC分类号： H03M13/27 , G06F3/06 , G06F11/10 , G06F11/16 , G06F11/30 , G06F13/42 , G06F16/11 , G06F16/182 , G06F16/2457 , G06F21/62 , G06F21/64 , H03M13/15 , H03M13/25 , H03M13/29 , H03M13/37 , H04L1/00 , H04L9/08 , H04L27/34 , H04L67/1097 , H04L67/63
CPC分类号： G06F11/108 , G06F3/0604 , G06F3/0605 , G06F3/061 , G06F3/0619 , G06F3/0622 , G06F3/0643 , G06F3/0644 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/0668 , G06F3/067 , G06F3/0689 , G06F11/1076 , G06F11/1662 , G06F11/3034 , G06F13/4282 , G06F16/122 , G06F16/1824 , G06F16/24578 , G06F21/6218 , G06F21/645 , H03M13/2906 , H03M13/3761 , H04L9/0861 , H04L67/1097 , H04L67/63 , G06F3/064 , G06F2201/805 , H03M13/1515
摘要： A storage network operates by: receiving a encoded data slice for storage by the storage network, wherein the encoded data slice is associated with a vault; generating a encryption key corresponding to the encoded data slice based on a vault identifier associated with the vault; utilizing the encryption key to generate a encrypted data slice and that corresponds to, and is based on, the encoded data slice; storing the encrypted data slice in a storage unit of the storage network; receiving a request to retrieve the encoded data slice; retrieving the encrypted data slice corresponding to the encoded data slice from the storage unit of the storage network; generating a decryption key corresponding to the encoded data slice based on the vault identifier, wherein the decryption key is different from the encryption key; and regenerating the encoded data slice using the decryption key.

88. 发明授权

US12093571B1 Accelerating request/response protocols 有权
公开(公告)号：US12093571B1
公开(公告)日：2024-09-17
申请号：US17937167
申请日：2022-09-30
申请人： Amazon Technologies, Inc.
发明人： Evgeny Schmeilin , Leah Shalev , Ghanim Fodi , Shay Agroskin , Gilad Broner
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0668
摘要： A network device can be used on a client side and a server side to accelerate request/response protocols for object transfers between the client side and the server side. The network device can interface with an application executing on the host device, which can allow the network device to expose different operations that can enable acceleration of different higher level object transfer commands. The network device can expose operations to pre-post anonymous receive buffers and client buffers even before the server side responds to the object transfer commands, which can allow the client buffers to be available to the server early on. Small transfers can be performed without remote direct memory access (RDMA) and can be received in the anonymous receive buffers at the server side. Bulk object data can be sent via RDMA for direct data placement into the client buffers to enable zero copy.

89. 发明授权

US10073736B2 Proxying slice access requests during a data evacuation 有权
公开(公告)号：US10073736B2
公开(公告)日：2018-09-11
申请号：US15220983
申请日：2016-07-27
申请人： International Business Machines Corporation
发明人： Asimuddin Kazi , Niall J. McShane , Manish Motwani , Michael J. Niedbala
IPC分类号： G06F3/06 , G06F11/10 , H04L29/06 , G06F17/30 , H04L29/08 , G06F11/16 , G06F13/42 , G06F21/62 , H04L9/08 , H03M13/29 , H03M13/37 , G06F21/64 , H03M13/15
CPC分类号： G06F11/108 , G06F3/0604 , G06F3/0605 , G06F3/061 , G06F3/0619 , G06F3/0622 , G06F3/064 , G06F3/0643 , G06F3/0644 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/0668 , G06F3/067 , G06F3/0689 , G06F11/1076 , G06F11/1662 , G06F11/3034 , G06F13/4282 , G06F16/122 , G06F16/1824 , G06F16/24578 , G06F21/6218 , G06F21/645 , G06F2201/805 , H03M13/1515 , H03M13/2906 , H03M13/3761 , H04L9/0861 , H04L63/0428 , H04L63/061 , H04L63/0853 , H04L63/108 , H04L67/1097 , H04L67/327
摘要： A method begins by a processing module receiving a checked write slice request from a requesting entity. The method continues by determining that locally stored encoded data slices do not include the requested encoded data slice. The method continues by identifying an alternate location for the requested encoded data slice. The method continues by determining whether the alternate location is associated with storage of the encoded data slice. The method continues when the alternate location is associated with the storage of the encoded data slice, by issuing a favorable checked write slice response to a requesting entity. The method can include facilitating transfer of the requested encoded data slice from the alternate location to the storage unit for storage.

90. 发明授权

US09971688B2 Apparatus and method for accelerating operations in a processor which uses shared virtual memory 有权
公开(公告)号：US09971688B2
公开(公告)日：2018-05-15
申请号：US15394539
申请日：2016-12-29
申请人： Intel Corporation
发明人： Eliezer Weissmann , Karthikeyan Karthik Vaithianathan , Yoav Zach , Boris Ginzburg , Ronny Ronen
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/1027 , G06F12/1009 , G06F3/06 , G06F12/02
CPC分类号： G06F12/0811 , G06F3/0646 , G06F3/0662 , G06F3/0668 , G06F9/3851 , G06F9/3881 , G06F9/3887 , G06F12/0292 , G06F12/084 , G06F12/0875 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F12/1072 , G06F12/1081 , G06F12/1441 , G06F12/145 , G06F2212/1024 , G06F2212/283 , G06F2212/302 , G06F2212/452 , G06F2212/60 , G06F2212/62 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

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