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81. 发明申请

WO2016186850A1 REAL-TIME CACHE BEHAVIOR FORECAST USING HYPOTHETICAL CACHE 审中-公开
标题翻译：实时高速缓存行为预测使用HYPOTHETICAL CACHE
公开(公告)号：WO2016186850A1
公开(公告)日：2016-11-24
申请号：PCT/US2016/030895
申请日：2016-05-05
申请人： QUALCOMM INCORPORATED
发明人： PARK, Hee Jun , RYCHLIK, Bohuslav , THOMSON, Steven S.
IPC分类号： G06F12/08 , G06F17/50 , G06F12/0802
CPC分类号： G06F12/0864 , G06F12/0802 , G06F12/0811 , G06F12/1027 , G06F17/5022 , G06F2212/283 , G06F2212/6032 , G06F2212/684
摘要： Systems and methods for forecasting behavior of caches include a hypothetical cache. The hypothetical cache is configured to emulate cache behavior, and performance metrics for the hypothetical cache are determined, where the performance metrics may be based on cache hits/misses. Performance metrics for a real cache of a processor core of a processing system may also be similarly determined. Behavior of the real cache is forecast based, at least, on performance metrics of the hypothetical cache, and in some cases, also on performance metrics of the real cache (e.g., based on a comparison of the performance metrics). Actions may be recommended and/or performed based on the forecast, where the actions include modifying the real cache size, associativity, or allocation for processor cores, migrating a task running in one processor cluster to another processor cluster, or for collecting data for the real cache for offline analysis.
摘要翻译：用于预测缓存行为的系统和方法包括假设的缓存。假设高速缓存被配置为模拟缓存行为，并且确定假设高速缓存的性能度量，其中性能度量可以基于缓存命中/未命中。也可以类似地确定处理系统的处理器核心的实际高速缓存的性能度量。至少基于假设高速缓存的性能指标，以及在某些情况下，也可以基于实际高速缓存的性能度量（例如，基于性能指标的比较）来预测真实缓存的行为。可以基于预测推荐和/或执行动作，其中动作包括修改处理器核心的实际高速缓存大小，关联性或分配，将在一个处理器集群中运行的任务迁移到另一个处理器集群，或者为真正的缓存用于离线分析。

82. 发明申请

WO2016064403A1 SUPERVISORY MEMORY MANAGEMENT UNIT 审中-公开
标题翻译：监督记忆管理单位
公开(公告)号：WO2016064403A1
公开(公告)日：2016-04-28
申请号：PCT/US2014/061965
申请日：2014-10-23
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： SHERLOCK, Derek A.
IPC分类号： G06F12/00 , G06F11/07 , G06F11/30
CPC分类号： G06F12/1027 , G06F11/073 , G06F11/0793 , G06F12/1009 , G06F12/1081 , G06F12/145 , G06F12/1466 , G06F2212/1052 , G06F2212/651 , G06F2212/657 , G06F2212/681 , G06F2212/684
摘要： A system includes a central processing unit (CPU) to process data with respect to a virtual address generated by the CPU. A first memory management unit (MMU) translates the virtual address to a physical address of a memory with respect to the data processed by the CPU. A supervisory MMU translates the physical address of the first MMU to a storage address for storage and retrieval of the data in the memory. The supervisory MMU controls access to the memory via the storage address generated by the first MMU.
摘要翻译：系统包括中央处理单元（CPU），用于处理关于由CPU生成的虚拟地址的数据。第一存储器管理单元（MMU）将虚拟地址相对于由CPU处理的数据转换为存储器的物理地址。监控MMU将第一MMU的物理地址转换为存储地址，以存储和检索存储器中的数据。监控MMU通过由第一MMU生成的存储地址来控制对存储器的访问。

83. 发明申请

WO2015061744A1 ORDERING AND BANDWIDTH IMPROVEMENTS FOR LOAD AND STORE UNIT AND DATA CACHE 审中-公开
标题翻译：装载和存储单元和数据缓存的订购和带宽改进
公开(公告)号：WO2015061744A1
公开(公告)日：2015-04-30
申请号：PCT/US2014/062267
申请日：2014-10-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： KUNJAN, Thomas , BINGHAM, Scott, T. , EVERS, Marius , WILLIAMS, James, D.
IPC分类号： G06F9/38 , G06F9/312 , G06F12/08
CPC分类号： G06F9/30043 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F12/0875 , G06F12/1027 , G06F2212/452 , G06F2212/684
摘要： The present invention provides a method and apparatus for supporting embodiments of an out-of-order load to load queue structure. One embodiment of the apparatus includes a load queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes a load order queue for cacheable operations that ordered for a particular address.
摘要翻译：本发明提供了一种用于支持负载队列结构的无序负载的实施例的方法和装置。该装置的一个实施例包括用于存储适于相对于其他存储器操作无序执行的存储器操作的加载队列。该装置还包括针对特定地址排序的可缓存操作的加载顺序队列。

84. 发明申请

WO2014042747A1 CONCURRENT CONTROL FOR A PAGE MISS HANDLER 审中-公开
标题翻译：页面错误处理的并发控制
公开(公告)号：WO2014042747A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/048594
申请日：2013-06-28
申请人： INTEL CORPORATION
发明人： HILDESHEIM, Gur , TAN, Chang Kian , CHAPPELL, Robert S. , BHATIA, Rohit
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/10 , G06F12/1027 , G06F2212/1024 , G06F2212/651 , G06F2212/655 , G06F2212/681 , G06F2212/684
摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并从寻呼结构获得物理地址的对应部分，与第一步行者同时操作的第二步行者，用于防止第一步行器响应于匹配由第二步行者访问的并行寻呼结构的对应的线性地址部分的第一线性地址部分而将所获得的物理地址部分存储在寻呼缓存中的逻辑。描述和要求保护其他实施例。

85. 发明申请

WO2013143784A1 HYBRID ADDRESS TRANSLATION 审中-公开
标题翻译：混合地址翻译
公开(公告)号：WO2013143784A1
公开(公告)日：2013-10-03
申请号：PCT/EP2013/053287
申请日：2013-02-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： GSCHWIND, Michael, Karl , BYBELL, Anthony, Joseph
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0292 , G06F12/1018 , G06F12/1036 , G06F2212/1016 , G06F2212/651 , G06F2212/684
摘要： Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.
摘要翻译：本发明的实施例涉及混合地址转换。本发明的一个方面包括接收第一地址，第一地址引用第一地址空间中的位置。计算机搜索段后备缓冲器（SLB）用于对应于第一地址的SLB条目; SLB条目包括类型字段和地址字段，并且确定SLB条目中的类型字段的值是否指示散列页表（HPT）搜索或基数树搜索。基于确定类型字段的值指示HPT搜索，搜索HPT以确定第二地址，第二地址包括将第一地址转换为第二地址空间; 并且基于确定类型字段的值指示基数树搜索，搜索基数树以确定第二地址。

86. 发明公开

KR1020170029594A 메모리 관리 방법 및 장치, 및 메모리 컨트롤러 审中-实审
标题翻译：存储器管理方法和设备和存储器控制器
公开(公告)号：KR1020170029594A
公开(公告)日：2017-03-15
申请号：KR1020177003800
申请日：2015-07-22
申请人： 후아웨이 테크놀러지 컴퍼니 리미티드
发明人： 류야오 , 천리청 , 추이쩌한 , 천밍위
IPC分类号： G06F13/16 , G06F12/02 , G06F9/30
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/1016 , G06F2212/68 , G06F2212/681 , G06F2212/684 , G06F13/1673 , G06F9/30047 , G06F12/0292
摘要： 메모리관리방법및 장치가개시된다. 방법은, 스토리지관리장치가, 메모리를관리하는단계, 그리고페이지테이블이페치요청내에서운반된가상어드레스를포함하지않은것으로결정하는때, 메모리관리장치가, 운영시스템의인터럽트를트리거링하는대신에메모리를관리하는단계를포함하므로, 운영시스템의부하가감소될수 있다. 가상어드레스가유효한것으로결정하는때, 메모리관리장치는블랭크페이지를신청한다. 메모리관리장치는메모리컨트롤러내에위치하고물리메모리에더 가깝기때문에, 메모리관리효율이효과적으로향상될수 있다.
摘要翻译：一种内存管理方法和设备。该方法包括：由存储器管理装置管理存储器; 当存储器管理装置确定页表不包括在存储器访问请求中携带的虚拟地址时，代替触发操作系统的中断，由存储器管理装置管理存储器，从而使得操作系统可以减少，其中当虚拟地址被确定为有效时，应用空白页面，并且存储器管理设备位于存储器控制器中并且更靠近物理存储器，使得存储器管理效率可以有效增加。

87. 发明公开

KR1020150128804A 하드웨어 테이블 워크를 수행하는데 요구된 시간 및 컴퓨팅 리소스들의 양을 감소시키기 위한 방법들 및 시스템들 审中-实审
标题翻译：减少时间和计算资源的方法和系统，需要执行硬件桌面
公开(公告)号：KR1020150128804A
公开(公告)日：2015-11-18
申请号：KR1020157027417
申请日：2014-03-04
申请人： 퀄컴 인코포레이티드
发明人： 정토마스 , 투즈니아제딘 , 쳉충렌 , 보스틀리필제이
IPC分类号： G06F12/10 , G06F9/455
CPC分类号： G06F12/1027 , G06F9/45533 , G06F9/45545 , G06F9/45558 , G06F12/10 , G06F2212/151 , G06F2212/171 , G06F2212/507 , G06F2212/654 , G06F2212/684
摘要： 변환색인버퍼 (TLB) 미스가발생할경우에하드웨어테이블워크 (HWTW) 를수행하는데요구된시간및 컴퓨팅리소스들의양을감소시키는컴퓨터시스템및 방법이제공된다. 스테이지 1 (SI) 페이지테이블이저장되는물리적어드레스 (PA) 를발견하기위해스테이지 2 (S2) HWTW 를수행할경우에 TLB 미스가발생하면, MMU 는중간물리적어드레스 (IPA) 를이용하여대응하는 PA 를예측하고, 이에의해, S2 테이블룩업들중 임의의룩업을수행하기위한필요성을회피시킨다. 이는이들타입들의 HWTW 판독트랜잭션들을수행할경우에수행될필요가있는룩업들의수를크게감소시키고, 이는이들타입들의트랜잭션들을수행하는것과연관된프로세싱오버헤드및 성능페널티들을크게감소시킨다.

88. 发明授权

KR100421749B1 비폴팅로드명령실행방법및그장치 失效
公开(公告)号：KR100421749B1
公开(公告)日：2004-05-17
申请号：KR1019960005517
申请日：1996-02-27
申请人： 선 마이크로시스템즈 인코퍼레이티드
发明人： 레슬리콘
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F12/1027 , G06F12/145 , G06F12/1458 , G06F2212/684
摘要： A non-fault-only (NFO) bit is included in the translation table entry for each page. If the NFO bit is set, non-faulting loads accessing the page will cause translations to occur. Any other access to the non-fault-only page is an error, and will cause the processor to fault. A non-faulting load behaves like a normal load except that it never produces a fault even when applied to a page with the NFO bit set. The NFO bit in a translation table entry marks a page that is mapped for safe access by non-faulting loads, but can still cause a fault by other, normal accesses. The NFO bit indicates which pages are illegal. Selected pages, such as the virtual page 0x0, can be mapped in the translation table. Whenever a null-pointer is dereferenced by a non-faulting load, a translation lookaside buffer (TLB) hit will occur, and zero will be returned immediately without trapping to software to find the requested page. A second embodiment provides that when the operating system software routine invoked by a TLB miss discovers that a non-faulting load has attempted to access an illegal virtual page that was not previously translated in the translation table, the operating system creates a translation table entry for that virtual page mapping it to a physical page of all zeros and asserting the NFO bit for that virtual page.
摘要翻译：每个页面的翻译表条目中都包含非故障（NFO）位。如果设置了NFO位，访问页面的非错误加载将导致翻译发生。对非故障页面的任何其他访问都是错误的，并且会导致处理器发生故障。非故障加载的行为与普通加载类似，不同之处在于，即使应用于设置了NFO位的页面，也不会产生故障。翻译表条目中的NFO位标记了一个页面，该页面被非错误加载映射为安全访问，但仍可能导致其他正常访问的错误。 NFO位指示哪些页面是非法的。所选页面（例如虚拟页面0x0）可以映射到转换表中。每当空指针被非错误加载解引用时，转换后备缓冲区（TLB）命中将会发生，并且零将立即返回，而不会陷入到软件中以找到所请求的页面。第二实施例规定，当由TLB未命中调用的操作系统软件例程发现非错误加载已尝试访问先前未在翻译表中翻译的非法虚拟页面时，操作系统创建用于该虚拟页面将其映射到全零的物理页面并断言该虚拟页面的NFO位。＆lt;图像＆GT;

89. 发明公开

EP3211534A4 DATA PROCESSING METHOD, MEMORY MANAGEMENT UNIT AND MEMORY CONTROL DEVICE 有权
公开(公告)号：EP3211534A4
公开(公告)日：2017-12-13
申请号：EP15886776
申请日：2015-03-27
申请人： HUAWEI TECH CO LTD
发明人： CHEN YUN , ZHANG GUANGFEI , SONG KUNPENG
IPC分类号： G06F12/10 , G06F12/1009 , G06F12/1027
CPC分类号： G06F12/1027 , G06F12/10 , G06F12/1009 , G06F2212/1024 , G06F2212/65 , G06F2212/68 , G06F2212/684
摘要： Embodiments of the present invention disclose a data processing method, including: receiving, by a memory management unit, a virtual address; determining, by the memory management unit, that the virtual address does not hit a translation look-aside buffer, and reading a page table base address register to obtain a page table base address; obtaining, by the memory management unit according to the page table base address, an identifier ID of a memory control device corresponding to the page table base address, sending the virtual address, the page table base address, and the ID of the memory control device to the memory control device; and receiving, by the memory management unit, a physical address that is sent by the memory control device and that is corresponding to the virtual address, and updating the translation look-aside buffer according to the physical address. In the data processing method, a page table walk operation is executed by only a memory control device, thereby reducing a burden caused by the page table walk operation to an on-chip communications network.

90. 发明公开

EP3121731A4 MEMORY MANAGEMENT METHOD AND DEVICE 有权
标题翻译： SPEICHERVERWALTUNGSVERFAHREN UND -VORRICHTUNG
公开(公告)号：EP3121731A4
公开(公告)日：2017-04-26
申请号：EP15789083
申请日：2015-04-15
申请人： HUAWEI TECH CO LTD
发明人： LIU YAO , HUANG YONGBING , CHEN MINGYU , CUI ZEHAN , CHEN LICHENG , RUAN YUAN
IPC分类号： G06F12/08 , G06F3/06 , G06F12/1009 , G06F12/1027
CPC分类号： G06F12/1027 , G06F3/0608 , G06F3/0619 , G06F3/0647 , G06F3/0652 , G06F3/0664 , G06F3/0685 , G06F12/1009 , G06F2212/1024 , G06F2212/684
摘要： Embodiments of the present invention provide a memory management method and a device, where the method includes: receiving, by a memory manager, a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if the memory manager finds, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating, by the memory manager, a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating, by the memory manager, the page table entry corresponding to the virtual address to the memory and the TLB. By determining the page fault type of the virtual address, the memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, the method in the embodiments can reduce a quantity of occurrences of the page fault, thereby improving memory management efficiency.
摘要翻译：本发明实施例提供一种内存管理方法及装置，所述方法包括：内存管理器接收内存访问请求，所述内存访问请求携带虚拟地址; 如果所述存储器管理器在翻译后备缓冲器TLB和存储器中找到与所述虚拟地址对应的页表项，则确定所述虚拟地址的页面错误类型; 如果虚拟地址的页面错误类型是空白页面引起的页面错误，则由存储器管理器将相应的页面分配给虚拟地址，其中空白页面引起的页面错误意味着没有相应的页面被分配给虚拟地址; 所述内存管理器将所述虚拟地址对应的页表条目更新至所述内存和所述TLB。通过确定虚拟地址的页面错误类型，当发生空白页面引起的页面错误时，内存管理器不会产生页面错误，而是将相应的页面分配给虚拟地址。因此，本实施例的方法可以减少页面错误的发生数量，从而提高内存管理效率。

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