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    • 82. 发明申请
    • DIGITAL PHASE-LOCKED LOOP ARCHITECTURE
    • 数字锁相环路结构
    • WO2010118980A1
    • 2010-10-21
    • PCT/EP2010/054599
    • 2010-04-07
    • CAMBRIDGE SILICON RADIO LIMITEDSORNIN, Nicolas
    • SORNIN, Nicolas
    • H03L7/081H03L7/091H03C3/09
    • H03L7/081H03L7/091
    • A phase-locked loop circuit comprising: an oscillator (20) configured to generate an output signal; an input (25) for receiving a reference clock signal; a delay cell (26) configured to delay the reference clock signal to generate a delayed reference clock signal; a phase comparator (27) configured to generate a quantised signal indicative of the phase difference between the output signal and the delayed reference clock signal, an integrator (28) configured to integrate the quantised signal to form an integrated signal; a first feedback path (22) configured to control the phase and/or frequency of the oscillator in dependence on the integrated signal; and a second feedback path (23) configured to adjust the delay applied by the delay cell (26) in dependence on the integrated signal.
    • 一种锁相环电路,包括:振荡器(20),被配置为产生输出信号; 用于接收参考时钟信号的输入端(25); 延迟单元(26),被配置为延迟所述参考时钟信号以产生延迟的参考时钟信号; 相位比较器(27),被配置为产生指示所述输出信号和所述延迟的参考时钟信号之间的相位差的量化信号;积分器(28),被配置为将所述量化的信号积分以形成积分信号; 第一反馈路径(22),被配置为根据所述积分信号来控制所述振荡器的相位和/或频率; 以及第二反馈路径(23),被配置为根据所述积分信号调整由所述延迟单元(26)施加的延迟。
    • 84. 发明申请
    • RADIO APPARATUS
    • 无线电设备
    • WO2010086207A1
    • 2010-08-05
    • PCT/EP2010/050212
    • 2010-01-11
    • CAMBRIDGE SILICON RADIO LIMITEDTHOUKYDIDES, Alexander
    • THOUKYDIDES, Alexander
    • H04L29/06H04W72/12G10L11/02
    • H04W72/082G10L25/78H04L1/1829H04L1/22H04L69/18H04W72/1215H04W72/1242H04W88/06
    • A radio apparatus comprising : a first transceiver means arranged to receive and transmit packets according to a first protocol; a second transceiver means arranged to receive or transmit packets according to a second, different protocol, the second transceiver means being located such that interference is possible between packets of the first and second protocols; analysing means for determining a probability that a packet to be transmitted or received by the first transceiver means does not contain only redundant information; and decision means for making a decision based on the determined probability as to whether or not the packet should be respectively transmitted or received. The first transceiver means is arranged to respectively transmit or receive the packet or not according to the decision.
    • 一种无线电设备,包括:第一收发器装置,被布置为根据第一协议接收和发送分组; 第二收发器装置,被布置为根据第二不同协议接收或发送分组,所述第二收发器装置被定位成使得可能在所述第一和第二协议的分组之间进行干扰; 用于确定由第一收发器装置发送或接收的分组不仅包含冗余信息的概率的分析装置; 以及用于基于所确定的概率来决定是否应该分别发送或接收分组的决定装置。 第一收发器装置被配置为根据该决定分别发送或接收分组。
    • 85. 发明申请
    • SIGNAL RECEPTION
    • WO2010060734A3
    • 2010-06-03
    • PCT/EP2009/064422
    • 2009-11-02
    • CAMBRIDGE SILICON RADIO LIMITEDYU, ChunyangPOPESCU, Andrei
    • YU, ChunyangPOPESCU, Andrei
    • H03M13/45H03M13/13
    • A method of receiving a demodulated waveform according to a protocol in which the waveform represents a block of transmitted bits comprising a first group of bits and a second group of bits, the second group of bits being a function of the first group of bits, the method comprising: sampling the demodulated waveform to recover a first group of sample values corresponding to the first group of transmitted bits and a second group of sample values corresponding to the second group of transmitted bits; assigning bit values to reliable sample values of the first group of sample values; generating a set of candidates for a block of bits corresponding to the demodulated waveform, each candidate comprising a first group of candidate bits and a second group of candidate bits, the first group of candidate bits being generated using the assigned bit values and a combination of bit values unique to that candidate in the set of candidates, and the second group of candidate bits being generated by applying the said function to the first group of candidate bits; performing a correlation operation by determining a correlation between each candidate and the recovered first and second groups of sample values to form a correlation value associated with each candidate; and selecting the candidate associated with the correlation value that is indicative of the strongest degree of correlation between a candidate and the first and second groups of sample values to be the block of bits corresponding to the demodulated waveform.
    • 86. 发明申请
    • ESD PROTECTION
    • ESD保护
    • WO2010043485A1
    • 2010-04-22
    • PCT/EP2009/062513
    • 2009-09-28
    • CAMBRIDGE SILICON RADIO LIMITEDPUGSLEY, WilliamPENFOLD, JustinSABBERTON, Ian
    • PUGSLEY, WilliamPENFOLD, JustinSABBERTON, Ian
    • H01L27/02H03K19/003
    • H03K19/00315H01L27/0285
    • A circuit for protecting a node (201) in an electronic device (200) from an electrostatic discharge comprising: a voltage rail (206) arranged to provide an predetermined voltage when the device is powered; a first switching device (202) connected between said node (201) and ground (204); a second switching device (203) coupled to said node (201) and arranged to control the conductance of the first switching device (202) between said node (201) and ground (204); wherein, the second switching device (203) is configured to, irrespective of whether the device is powered or not powered, (a) hold the conductance of the first switching device (202) low when the potential difference between the node (201) and the voltage rail (206) is within an operating range, and (b) hold the conductance of the first switching device (202) high in response to an overvoltage at the node (201) so as to allow current to flow from the node (201) to ground (204).
    • 一种用于保护电子设备(200)中的节点(201)免受静电放电的电路,包括:电压轨(206),布置成当所述设备被供电时提供预定电压; 连接在所述节点(201)和地(204)之间的第一开关装置(202); 耦合到所述节点(201)并被布置成控制所述节点(201)和地(204)之间的第一开关装置(202)的电导的第二开关装置(203)。 其中,所述第二交换装置(203)被配置为:无论所述装置是供电还是未供电,(a)当所述节点(201)与所述节点(201)之间的电位差保持为低时,保持所述第一开关装置 电压轨(206)处于工作范围内,(b)响应于节点(201)处的过电压而使第一开关装置(202)的电导保持高电平,以允许电流从节点( 201)到地面(204)。
    • 89. 发明申请
    • PHASE-LOCKED LOOP MODULATION
    • 相位锁定调制
    • WO2009121702A1
    • 2009-10-08
    • PCT/EP2009/052963
    • 2009-03-13
    • CAMBRIDGE SILICON RADIO LIMITEDLAMANNA, PasqualeSORNIN, Nicolas
    • LAMANNA, PasqualeSORNIN, Nicolas
    • H03L7/197
    • H04L7/0331H03L7/08H03L7/1976
    • A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; the output data to form a divided signal a division ratio controller configured to, when clocked by an input signal, generate a series of output data for forming the division control signal; the phase-locked loop having: a first mode of operation in which the frequency divider is operable to frequency divide the output of the oscillator by a value dependent on the output of the division ratio controller; and a second mode of operation in which the frequency divider is not operable to frequency divide the output of the oscillator by a value dependent on the output of the division ratio controller, and the division ratio controller is clocked by a signal that is independent of the output of the oscillator.
    • 一种锁相环,具有:形成振荡输出信号的振荡器; 连接用于接收振荡器的输出的分频器,并将其除频依赖于除法控制信号的值; 以及相位比较器,用于比较分频信号的相位和参考信号以产生控制信号,振荡器的操作取决于控制信号; 所述输出数据形成分频信号,分频比控制器,被配置为当由输入信号计时时,产生用于形成分频控制信号的一系列输出数据; 所述锁相环具有:第一操作模式,其中所述分频器可操作以将所述振荡器的输出频率除以取决于所述分频比控制器的输出的值; 以及第二操作模式,其中分频器不可操作以将振荡器的输出频率除以取决于分频比控制器的输出的值,并且分频比控制器由独立于 输出振荡器。
    • 90. 发明申请
    • PROTOCOL COEXISTENCE
    • 协议共同体
    • WO2009112559A2
    • 2009-09-17
    • PCT/EP2009/052947
    • 2009-03-12
    • CAMBRIDGE SILICON RADIO LIMITEDTHOUKYDIDES, Alexander
    • THOUKYDIDES, Alexander
    • H04L69/18H04L67/04H04L69/40H04M1/2535H04M1/6066H04M2250/02H04W88/06
    • A communication device having: a first communication unit for transmitting and/or receiving by a first protocol acknowledgements for data received by the device; a second communication unit for transmitting data units of a second protocol, the first and second protocols being such that the data units of the second protocol can interfere with the acknowledgements of the first protocol; and a controller configured to control the device such that, when a data unit of the second protocol is being transmitted by the second communication unit and the first communication unit is to transmit or receive an acknowledgement of the first protocol: the second communication unit interrupts the transmission of the data unit of the second protocol, the first communication unit transmits or receives the acknowledgement of the first protocol and the second transmitter resumes transmission of the data unit of the second protocol from the point that transmission of the data unit would have reached if it had not been interrupted.
    • 一种通信设备,具有:第一通信单元,用于通过由所述设备接收的数据的第一协议确认发送和/或接收; 第二通信单元,用于发送第二协议的数据单元,所述第一和第二协议使得所述第二协议的数据单元可以干扰所述第一协议的确认; 以及控制器,被配置为控制所述设备,使得当所述第二协议的数据单元正由所述第二通信单元发送时,所述第一通信单元要发送或接收所述第一协议的确认时,所述第二通信单元中断 第二协议的数据单元的传输,第一通信单元发送或接收第一协议的确认,并且第二发射机从数据单元的传输将到达第二协议的数据单元的传输,如果 它没有中断。