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81. 发明申请

US20110260264A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110260264A1
公开(公告)日：2011-10-27
申请号：US12937321
申请日：2010-06-28
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823871 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/6656
摘要： There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation. According to the present invention, it is possible not only to reduce the gate resistance, but also to eliminate difficulties in forming contact holes by RIE at the gate and source/drain regions.
摘要翻译：提供了一种半导体器件及其制造方法。根据本发明的制造半导体器件的方法包括：在半导体衬底上形成包括栅极和源极和漏极区域的晶体管结构; 进行第一硅化，以在源区和漏区上形成第一金属硅化物层; 在所述衬底上沉积第一介电层，所述第一介电层的顶部与所述栅极区的顶部齐平; 在与第一电介质层中的源极和漏极区对应的部分处形成接触孔; 并且在所述栅极区和所述接触孔中进行第二硅化以形成第二金属硅化物，其中形成所述第一金属硅化物层以防止在所述第二硅化期间在所述源极和漏极区发生硅化。根据本发明，不仅可以降低栅极电阻，而且可以消除在栅极和源极/漏极区域通过RIE形成接触孔的困难。

82. 发明申请

US20110260262A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110260262A1
公开(公告)日：2011-10-27
申请号：US12999796
申请日：2010-09-17
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/8232
CPC分类号： H01L21/823468 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： A semiconductor device includes a semiconductor substrate; gates, spacers on both sides of the respective gates, and source and gain regions on both sides of the respective spacers, which are formed on the semiconductor substrate; lower contacts located on the respective source and gain regions and abutting outer-sidewalls of the spacers, with bottoms covering at least a portion of the respective source and gain regions; an inter-layer dielectric layer formed on the gates, the spacers, the source and gain regions, and the lower contacts, wherein the respective source and gain regions of each of the transistor structures are isolated from each other by the inter-layer dielectric layer; and upper contacts formed in the inter-layer dielectric layer and corresponding to the lower contacts. Methods for fabricating such a semiconductor device and for manufacturing contacts for semiconductor devices.
摘要翻译：半导体器件包括半导体衬底; 各个栅极的两侧的栅极，间隔物，以及形成在半导体衬底上的各个间隔物的两侧的源极和增益区域; 下部触点位于相应的源极和增益区域以及邻接的间隔物的外侧壁上，底部覆盖相应的源极和增益区域的至少一部分; 形成在栅极，间隔物，源极和增益区域以及下部触点上的层间电介质层，其中每个晶体管结构的各个源极和增益区域通过层间电介质层彼此隔离 ; 以及形成在层间电介质层中并对应于下触点的上触点。用于制造这种半导体器件和用于制造用于半导体器件的触点的方法。

83. 发明申请

US20110227144A1 HIGH-PERFORMANCE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：高性能半导体器件及其制造方法
公开(公告)号：US20110227144A1
公开(公告)日：2011-09-22
申请号：US12999086
申请日：2010-06-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/495 , H01L21/26513 , H01L21/2652 , H01L21/2658 , H01L21/26586 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66492 , H01L29/66545
摘要： The present invention relates to a method of manufacturing a semiconductor device, and the method uses the mode of thermal annealing the source/drain regions and performing Halo ion implantation to form a Halo ion-implanted region by: first removing the dummy gate to expose the gate dielectric layer to form an opening; then performing a tilted Halo ion implantation to the device from the opening to form a Halo ion-implanted region on both sides of the channel of the semiconductor device; and then annealing to activate the dopants in the Halo ion-implanted region; finally performing subsequent process to the device according to the requirement of the manufacture process. Through the present invention, the dopants in the Halo ion-implanted region improperly introduced to the source region and the drain region may be reduced, and then the overlap between the Halo ion-implantation region and the dopant region of the source/drain regions may be reduced, thus to reduce the band-band leakage current in the MOSFET, and hence improve the performance of the device.
摘要翻译：本发明涉及一种制造半导体器件的方法，该方法使用对源/漏区进行热退火的方式，并进行Halo离子注入以形成Halo离子注入区域，方法是首先去除伪栅极以暴露出栅介电层形成开口; 然后从所述开口对所述器件进行倾斜的Halo离子注入，以在所述半导体器件的沟道的两侧上形成Halo离子注入区域; 然后退火以激活卤素离子注入区域中的掺杂剂; 最后根据制造过程的要求对设备进行后续处理。通过本发明，可以减少不适当地引入源极区域和漏极区域的卤素离子注入区域中的掺杂剂，然后卤素离子注入区域和源极/漏极区域的掺杂剂区域之间的重叠可以减小，从而降低MOSFET中的带带漏电流，从而提高器件的性能。

84. 发明授权

US07897468B1 Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island 有权
标题翻译：具有通过背面工程形成的自对准双门的装置，以及具有超陡峭退化岛的装置
公开(公告)号：US07897468B1
公开(公告)日：2011-03-01
申请号：US12556604
申请日：2009-09-10
申请人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/1083 , H01L29/165 , H01L29/66484 , H01L29/6659 , H01L29/66636 , H01L29/66742 , H01L29/7831 , H01L29/78648
摘要： A method of forming a dual gate semiconductor device is provided that includes providing a substrate having a first semiconductor layer and a second semiconductor layer, in which a first gate structure is formed on the second semiconductor layer. The second semiconductor layer and the first semiconductor layer are etched to expose the substrate using the first gate structure as an etch mask. A remaining portion of the first semiconductor layer is present underlying the first gate structure having edges aligned to the edges of the first gate structure. An epitaxial semiconductor material is formed on exposed portions of the substrate. The substrate and the remaining portion of the first semiconductor layer are removed to provide a recess having edges aligned to the edges of the first gate structure, and a second gate structure is formed in the recess. A method of forming a retrograded island is also provided.
摘要翻译：提供一种形成双栅极半导体器件的方法，其包括提供具有第一半导体层和第二半导体层的衬底，其中在第二半导体层上形成第一栅极结构。蚀刻第二半导体层和第一半导体层以使用第一栅极结构作为蚀刻掩模来露出衬底。第一半导体层的剩余部分位于具有与第一栅极结构的边缘对准的边缘的第一栅极结构下方。在衬底的暴露部分上形成外延半导体材料。去除衬底和第一半导体层的剩余部分以提供具有与第一栅极结构的边缘对准的边缘的凹部，并且在凹部中形成第二栅极结构。还提供了形成退火岛的方法。

85. 发明授权

US09373722B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09373722B2
公开(公告)日：2016-06-21
申请号：US14395076
申请日：2012-05-10
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/266 , H01L29/06 , H01L29/16 , H01L29/161 , H01L29/66 , H01L21/84 , H01L27/12 , H01L21/265 , H01L29/165
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/266 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/7849
摘要： The present invention provides a semiconductor structure comprising: a semiconductor base located on an insulating layer, wherein the insulating layer is located on a semiconductor substrate; source/drain regions, which are in contact with first sidewalls of the semiconductor base opposite to each other; gates located on second sidewalls of the semiconductor base opposite to each other; an insulating via located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer sandwiched between the insulating via and the semiconductor base. The present invention further provides a method for manufacturing a semiconductor structure comprising: forming an insulating layer on a semiconductor substrate; forming a semiconductor base on the insulating layer; forming a void within the semiconductor base, wherein the void exposes the semiconductor substrate; forming an epitaxial layer in the void through selective epitaxy; and forming an insulating via within the void. Short-channel effects are significantly suppressed through forming super-steep retrograde well (SSRW).
摘要翻译：本发明提供一种半导体结构，包括：位于绝缘层上的半导体基底，其中所述绝缘层位于半导体衬底上; 源极/漏极区域，其与半导体基板的彼此相对的第一侧壁接触; 位于半导体基板的彼此相对的第二侧壁上的门; 位于绝缘层上并嵌入到半导体基底中的绝缘通孔; 以及夹在绝缘通孔和半导体基底之间的外延层。本发明还提供一种用于制造半导体结构的方法，包括：在半导体衬底上形成绝缘层; 在绝缘层上形成半导体基底; 在所述半导体基底内形成空隙，其中所述空隙暴露所述半导体衬底; 通过选择性外延在空隙中形成外延层; 并在空隙内形成绝缘通孔。通过形成超陡逆行井（SSRW），短通道效应被显着抑制。

86. 发明授权

US09082717B2 Isolation region, semiconductor device and methods for forming the same 有权
标题翻译：隔离区，半导体器件及其形成方法
公开(公告)号：US09082717B2
公开(公告)日：2015-07-14
申请号：US13119129
申请日：2011-02-18
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/16 , H01L21/336 , H01L21/31 , H01L21/308 , H01L21/762 , H01L29/66 , H01L29/78
CPC分类号： H01L21/3083 , H01L21/76232 , H01L29/66636 , H01L29/78
摘要： An isolation region is provided. The isolation region includes a first groove and an insulation layer filling the first groove. The first groove is embedded into a semiconductor substrate and includes a first sidewall, a bottom surface and a second sidewall that extends from the bottom surface and joins to the first sidewall. An angle between the first sidewall and a normal line of the semiconductor substrate is larger than a standard value. A method for forming an isolation region is further provided. The method includes: forming a first trench on a semiconductor substrate, wherein an angle between a sidewall of the first trench and a normal line of the semiconductor substrate is larger than a standard value; forming a mask on the sidewall to form a second trench on the semiconductor substrate by using the mask; and forming an insulation layer to fill the first and second trenches. A semiconductor device and a method for forming the same are still further provided. In the semiconductor device, a material of the semiconductor substrate is interposed between a second groove bearing a semiconductor layer for forming an S/D region and the first and second sidewalls. The present invention is beneficial to reduce leakage current.
摘要翻译：提供隔离区域。隔离区域包括第一凹槽和填充第一凹槽的绝缘层。第一凹槽被嵌入到半导体衬底中，并且包括从底表面延伸并连接到第一侧壁的第一侧壁，底表面和第二侧壁。半导体衬底的第一侧壁和法线之间的角度大于标准值。还提供了形成隔离区域的方法。该方法包括：在半导体衬底上形成第一沟槽，其中第一沟槽的侧壁和半导体衬底的法线之间的角度大于标准值; 在所述侧壁上形成掩模以通过使用所述掩模在所述半导体衬底上形成第二沟槽; 以及形成绝缘层以填充所述第一和第二沟槽。还提供一种半导体器件及其形成方法。在半导体器件中，半导体衬底的材料插入在用于形成S / D区域的半导体层的第二沟槽和第一和第二侧壁之间。本发明有益于减少漏电流。

87. 发明授权

US08957481B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08957481B2
公开(公告)日：2015-02-17
申请号：US13379407
申请日：2011-05-11
申请人： Huilong Zhu , Huicai Zhong , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Huicai Zhong , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/70 , H01L27/12 , H01L21/8238 , H01L21/336 , H01L21/308 , H01L21/762 , H01L29/78 , H01L29/66
CPC分类号： H01L21/3086 , H01L21/76224 , H01L21/76229 , H01L29/66636 , H01L29/7848
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost. By forming the contacts self-aligned with the gate, the method avoids misalignment and improves performance of the device while reducing a footprint of the device and lowering manufacture cost of the device.
摘要翻译：本申请公开了一种半导体结构及其制造方法。与传统的形成触点的方法相比，本公开减少了接触电阻，并且避免了栅极和接触插塞之间的短路，同时简化了制造工艺，增加了集成密度并降低了制造成本。根据本公开的制造方法，形成第二浅沟槽隔离件，其上表面高于源极/漏极区域的上表面。由栅极的侧壁间隔物，第二浅沟槽隔离件的侧壁间隔件和源极/漏极区域的上表面限定的区域形成为接触孔。通过用导电材料填充接触孔来形成触点。该方法省略了用于提供接触孔的蚀刻步骤，这降低了制造成本。通过形成与栅极自对准的触点，该方法避免了未对准并且提高了器件的性能，同时减少了器件的占地面积并降低了器件的制造成本。

88. 发明授权

US08906753B2 Semiconductor structure and method for manufacturing the same 有权
公开(公告)号：US08906753B2
公开(公告)日：2014-12-09
申请号：US13380857
申请日：2011-08-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/28 , H01L29/417 , H01L29/66 , H01L29/423 , H01L29/78
CPC分类号： H01L21/28008 , H01L29/41733 , H01L29/4232 , H01L29/66545 , H01L29/66643 , H01L29/66772 , H01L29/78 , H01L29/7839
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, forming a gate structure on the SOI substrate; etching an SOI layer of the SOI substrate and a BOX layer of the SOI substrate on both sides of the gate structure to form trenches, the trenches exposing the BOX layer and extending partly into the BOX layer; forming sidewall spacers on sidewalls of the trenches; forming inside the trenches a metal layer covering the sidewall spacers, wherein the metal layer is in contact with the SOI layer which is under the gate structure. Accordingly, the present invention further provides a semiconductor structure formed according to aforesaid method. The manufacturing method and the semiconductor structure according to the present invention make it possible to reduce capacitance between a metal layer and a body silicon layer of an SOI substrate when a semiconductor device is in operation, which is therefore favorable for enhancing performance of the semiconductor device.

89. 发明授权

US08835316B2 Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor 有权
标题翻译：具有初级和半导体衬垫的晶体管，晶体管的制造方法和包括晶体管的半导体芯片
公开(公告)号：US08835316B2
公开(公告)日：2014-09-16
申请号：US13378997
申请日：2011-08-09
申请人： Haizhou Yin , Jun Luo , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Jun Luo , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/3213 , H01L21/768 , H01L29/78 , H01L29/66 , H01L29/417 , H01L21/285
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/32139 , H01L21/76897 , H01L29/41775 , H01L29/665 , H01L29/6659
摘要： The disclosure provides a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. The transistor comprises: an active area, a gate stack, a primary spacer, and source/drain regions, wherein the active area is on a semiconductor substrate; the gate stack, the primary spacer, and the source/drain regions are on the active area; the primary spacer surrounds the gate stack; the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer. Wherein the transistor further comprises: a silicide spacer, wherein the silicide spacer is located at opposite sides of the primary spacer, and a dielectric material is filled between the two ends of the silicide spacer in the width direction of the gate stack, so as to isolate the source/drain regions from each other.
摘要翻译：本发明提供一种晶体管，一种晶体管的制造方法和一种包括该晶体管的半导体芯片。晶体管包括：有源区，栅极堆叠，初级间隔物和源/漏区，其中有源区在半导体衬底上; 栅极堆叠，初级间隔物和源极/漏极区域在有源区域上; 主要间隔物围绕栅极堆叠; 源极/漏极区域被嵌入有源区域中并且与主隔板的相对侧自对准。其中，所述晶体管还包括：硅化物间隔物，其中所述硅化物间隔物位于所述主间隔物的相对侧，并且电介质材料填充在所述硅化物间隔物的所述栅堆叠的宽度方向的两端之间，以便将源极/漏极区彼此隔离。

90. 发明授权

US08829621B2 Semiconductor substrate for manufacturing transistors having back-gates thereon 有权
标题翻译：用于制造其上具有背栅的晶体管的半导体衬底
公开(公告)号：US08829621B2
公开(公告)日：2014-09-09
申请号：US13696995
申请日：2011-11-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Huicai Zhong
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Huicai Zhong
IPC分类号： H01L21/70 , H01L27/12 , H01L21/84 , H01L27/092 , H01L21/74 , H01L21/762 , H01L29/786
CPC分类号： H01L27/12 , H01L21/743 , H01L21/762 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.
摘要翻译：本发明涉及半导体衬底，具有半导体衬底的集成电路及其制造方法。根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括：半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层，其中，在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔，以穿透所述第二绝缘材料层，以将所述第一导电材料层与第二导电材料层，每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。

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