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81. 发明申请

US20160306415A1 POWER EFFICIENT PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：US20160306415A1
公开(公告)日：2016-10-20
申请号：US15192134
申请日：2016-06-24
申请人： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
发明人： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
摘要： In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

82. 发明申请

US20160182345A1 END-TO-END DATACENTER PERFORMANCE CONTROL 有权
标题翻译：端到端数字表现控制
公开(公告)号：US20160182345A1
公开(公告)日：2016-06-23
申请号：US14581595
申请日：2014-12-23
申请人： Andrew J. Herdrich , Patrick Connor , Dinesh Kumar , Alexander W. Min , Ravishankar Iyer , Daniel J. Dahle , Kapil Sood , Jeffrey B. Shaw
发明人： Andrew J. Herdrich , Patrick Connor , Dinesh Kumar , Alexander W. Min , Ravishankar Iyer , Daniel J. Dahle , Kapil Sood , Jeffrey B. Shaw
IPC分类号： H04L12/26
CPC分类号： H04L43/50 , G06F12/0811 , G06F12/084 , G06F2212/152 , G06F2212/601 , H04L41/0896 , H04L41/5009 , H04L41/5025 , H04L41/5035 , H04L41/5096 , H04L43/16
摘要： In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance control. In various embodiments, an apparatus for computing may receive a datacenter performance target, determine an end-to-end datacenter performance level based at least in part on quality of service data collected from a plurality of nodes, and send a mitigation command based at least in part on a result of a comparison of the end-to-end datacenter performance level determined to the datacenter performance target. In various embodiments, the apparatus for computing may include one or more processors, a memory, a datacenter performance monitor to receive a datacenter performance target corresponding to a service level agreement, and a mitigation module to send a mitigation command based at least in part on a result of a comparison of an end-to-end datacenter performance level to a datacenter performance target.
摘要翻译：在实施例中，描述了与端对端数据中心性能控制相关联的装置，方法和存储介质（暂时性和非暂时性）。在各种实施例中，用于计算的装置可以接收数据中心性能目标，至少部分地基于从多个节点收集的服务质量数据来确定端对端数据中心性能级别，并且至少基于从多个节点收集的服务数据发送缓解命令部分原因是比较确定数据中心性能目标的端对端数据中心性能级别。在各种实施例中，用于计算的装置可以包括一个或多个处理器，存储器，用于接收与服务水平协议相对应的数据中心性能目标的数据中心性能监视器，以及缓解模块，用于至少部分地基于这是将端到端数据中心性能级别与数据中心性能目标进行比较的结果。

83. 发明授权

US08799902B2 Priority based throttling for power/performance quality of service 有权
标题翻译：基于优先级的电源/性能质量服务节制
公开(公告)号：US08799902B2
公开(公告)日：2014-08-05
申请号：US11786019
申请日：2007-04-09
申请人： Ramesh Kumar Illikkal , Ravishankar Iyer , Jaideep Moses , Don Newell , Tryggve Fossum
发明人： Ramesh Kumar Illikkal , Ravishankar Iyer , Jaideep Moses , Don Newell , Tryggve Fossum
IPC分类号： G06F9/46 , G06F1/00 , G06F1/26 , G06F1/32 , G06F15/173
CPC分类号： G06F9/5077 , G06F9/5094 , G06F2209/504 , Y02D10/22 , Y02D10/36
摘要： A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.
摘要翻译：这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。因此，在省电模式中，执行低优先级应用/任务的处理元件被降低到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。此外，利用逻辑潜在地追踪每个优先级别的资源的利用率，这允许电力管理者从资源本身的角度基于每个优先级的影响来确定工作点。此外，软件实体本身可以分配功率管理器执行的操作点。

84. 发明申请

US20140215240A1 Methods And Apparatuses For Controlling Thread Contention 审中-公开
公开(公告)号：US20140215240A1
公开(公告)日：2014-07-31
申请号：US14227680
申请日：2014-03-27
申请人： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
发明人： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
IPC分类号： G06F1/32
CPC分类号： G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
摘要： An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

85. 发明授权

US08645728B2 Methods and apparatuses for controlling thread contention 有权
标题翻译：用于控制线程争用的方法和装置
公开(公告)号：US08645728B2
公开(公告)日：2014-02-04
申请号：US13461956
申请日：2012-05-02
申请人： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
发明人： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F15/00
CPC分类号： G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
摘要： An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
摘要翻译：一种装置包括多个核心和耦合到核心的控制器。如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。

86. 发明申请

US20130262902A1 POWER EFFICIENT PROCESSOR ARCHITECTURE 有权
标题翻译：功率有效的处理器架构
公开(公告)号：US20130262902A1
公开(公告)日：2013-10-03
申请号：US13992361
申请日：2011-09-06
申请人： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
发明人： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
摘要： In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从加速器接收中断的方法，响应于该中断将恢复信号直接发送到小型核心，并向第一小型核心提供大型核心的执行状态的子集，以及确定小型核心是否可以处理与该中断有关的请求，如果该确定是肯定的，则执行与该小核心中的该请求相对应的操作，否则将大的核心执行状态和恢复信号提供给该大核心。描述和要求保护其他实施例。

87. 发明申请

US20130185370A1 EFFICIENT PEER-TO-PEER COMMUNICATION SUPPORT IN SOC FABRICS 有权
标题翻译： SOC框架中的高效对等通信支持
公开(公告)号：US20130185370A1
公开(公告)日：2013-07-18
申请号：US13810033
申请日：2012-01-13
申请人： Bin Li , Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal
发明人： Bin Li , Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal
IPC分类号： H04L12/58
CPC分类号： H04L51/04 , G06F13/4022 , G06F2213/0038 , H04L49/109 , H04L51/30
摘要： Methods and apparatus for efficient peer-to-peer communication support in interconnect fabrics. Network interfaces associated with agents are implemented to facilitate peer-to-peer transactions between agents in a manner that ensures data accesses correspond to the most recent update for each agent. This is implemented, in part, via use of non-posted “dummy writes” that are sent from an agent when the destination between write transactions originating from the agent changes. The dummy writes ensure that data corresponding to previous writes reach their destination prior to subsequent write and read transactions, thus ordering the peer-to-peer transactions without requiring the use of a centralized transaction ordering entity.
摘要翻译：互连结构中有效的对等通信支持的方法和设备。实现与代理相关联的网络接口以便于以确保数据访问对应于每个代理的最新更新的方式促进代理之间的对等事务。这部分是通过使用从代理发出的写入事务之间的目标之间从代理发送的未发布的“虚拟写入”来实现的。虚拟写入确保与之前的写入相对应的数据在后续写入和读取事务之前到达其目的地，从而排序对等事务，而不需要使用集中式事务排序实体。

88. 外观设计

USD673194S1 Cutting insert 有权
标题翻译：切削刀片
公开(公告)号：USD673194S1
公开(公告)日：2012-12-25
申请号：US29397042
申请日：2011-07-11
申请人： Jeffrey F. Kovac , Lewis Ray Morrison , Kumar Reddy Mylavaram Nikhilesh , Ravishankar Iyer
设计人： Jeffrey F. Kovac , Lewis Ray Morrison , Kumar Reddy Mylavaram Nikhilesh , Ravishankar Iyer

89. 发明申请

US20120233393A1 Scheduling Workloads Based On Cache Asymmetry 有权
标题翻译：基于缓存不对称的调度工作负载
公开(公告)号：US20120233393A1
公开(公告)日：2012-09-13
申请号：US13042547
申请日：2011-03-08
申请人： Xiaowei Jiang , Li Zhao , Ravishankar Iyer
发明人： Xiaowei Jiang , Li Zhao , Ravishankar Iyer
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F12/0842 , G06F9/46 , G06F9/4881 , G06F2209/483
摘要： In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.
摘要翻译：在一个实施例中，处理器包括第一高速缓存和第二高速缓存，与第一高速缓存相关联的第一核和与第二高速缓存相关联的第二核。高速缓存具有非对称尺寸，并且调度器可以至少部分地基于对至少一个线程的训练阶段期间获得的不对称性和结果高速缓存性能信息的认识来智能地将线程调度到核心。

90. 发明申请

US20120173907A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC C0-STATE CACHE RESIZING 有权
标题翻译：能量效率和能量守恒的方法，装置和系统，包括动态C0状态缓存
公开(公告)号：US20120173907A1
公开(公告)日：2012-07-05
申请号：US13341657
申请日：2011-12-30
申请人： Jaideep MOSES , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S.R. Degalahal
发明人： Jaideep MOSES , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S.R. Degalahal
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , G06F1/3287 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
摘要翻译：描述了用于设备的能量效率操作的系统，装置和方法的实施例。在一些实施例中，监视高速缓存的高速缓存性能指示符，并且确定基于高速缓存性能指示符的一个或多个高速缓存性能参数的集合。基于缓存性能参数与其节能目标的比较来缓存高速缓存大小，以达到最佳高速缓存大小，从而降低功耗。

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