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    • 81. 发明申请
    • Apparatus and method for computing SHA-1hash function
    • 用于计算SHA-1hash函数的装置和方法
    • US20050144204A1
    • 2005-06-30
    • US10917685
    • 2004-08-12
    • Yun LeeSung JunYoung ParkSang LeeYoung KimKyo II Chung
    • Yun LeeSung JunYoung ParkSang LeeYoung KimKyo II Chung
    • G06F7/06G06F7/00H04L9/32
    • H04L9/0643
    • An apparatus and method for computing a SHA-1 hash function value are provided. The apparatus includes a first register unit including a plurality of registers that store a first bit string of predetermined lengths for generation of a hash function value; a second register unit storing input data in units of second bit strings with predetermined lengths, and sequentially outputting the second bit strings; a third register unit performing an operation on the first bit string of the plurality of registers and the second bit strings output from the second register unit so as to generate and store a third bit string, and updating first-bit string of the plurality of registers based on the third bit string; and an adding unit combining the first bit string stored in the first register unit, the first bit string of the third bit string stored in the third register unit, and the original initial values stored in the first register unit so as to obtain a hash function value. Accordingly, it is possible to reduce the size of the apparatus and stably compute a hash function value at a high speed.
    • 提供了一种用于计算SHA-1散列函数值的装置和方法。 该装置包括:第一寄存器单元,包括多个寄存器,用于存储用于生成散列函数值的预定长度的第一位串; 第二寄存器单元,以预定长度的第二位串为单位存储输入数据,并顺序地输出第二位串; 第三寄存器单元,对所述多个寄存器中的第一位串执行操作,以及从所述第二寄存器单元输出的所述第二位串,以产生和存储第三位串,并且更新所述多个寄存器中的第一位串 基于第三位串; 以及添加单元,组合存储在第一寄存器单元中的第一位串,存储在第三寄存器单元中的第三位串的第一位串和存储在第一寄存器单元中的原始初始值,以获得散列函数 值。 因此,可以减小装置的尺寸并且可以高速稳定地计算散列函数值。
    • 85. 发明申请
    • Verb pattern automatic extension and verification apparatus and method for use in Korean-Chinese machine translation system
    • 动画模式自动扩展和验证装置和方法用于韩文 - 中文机器翻译系统
    • US20050137851A1
    • 2005-06-23
    • US10892268
    • 2004-07-16
    • Cheol RyuMunpyo HongSang ParkYoung Kim
    • Cheol RyuMunpyo HongSang ParkYoung Kim
    • G06F17/28
    • G06F17/2863
    • The present invention relates to a verb pattern automatic extension and verification apparatus for use in a Korean-Chinese machine translation system. The verb pattern automatic extension and verification apparatus automatically extracts the verb pattern source part that is not applied with the verb pattern contained in the current Korean and Chinese pattern dictionary, and automatically generates the new Korean-Chinese verb pattern based on Chinese target language. Meanwhile, the verb pattern automatic extension and verification apparatus according to the present invention automatically extends one newly generated Korean-Chinese verb pattern to a plurality of similar verb pattern candidates, and newly registers the newly-generated and extended Korean-Chinese verb patterns in the Korean and Chinese verb pattern dictionary database. Accordingly, it is possible to easily and automatically collect a large quantity of the Korean and Chinese verb patterns. Further, the translation rate of the Korean-Chinese machine translation system can be rapidly increased due to the automatically increasing verb patterns.
    • 本发明涉及一种用于韩国 - 中国机器翻译系统的动词模式自动扩展和验证装置。 动词模式自动扩展和验证装置自动提取不包含当前韩文和中文模式字典中的动词模式的动词模式源部分,并根据中文目标语言自动生成新韩语动词模式。 同时,根据本发明的动词模式自动扩展和验证装置将一个新生成的韩文 - 中文动词模式自动地扩展到多个类似的动词模式候选,并且将新生成的和扩展的韩文 - 中文动词模式新登录在 韩文和中文动词模式字典数据库。 因此,可以容易地且自动地收集大量的韩文和中文动词模式。 此外,由于动态模式的自动增加,韩文机翻译系统的翻译速度可以迅速提高。
    • 86. 发明申请
    • Method of making a MOS transistor
    • 制造MOS晶体管的方法
    • US20050127410A1
    • 2005-06-16
    • US11044331
    • 2005-01-27
    • Young Kim
    • Young Kim
    • H01L21/28H01L21/302H01L21/336H01L21/461H01L29/49H01L29/76
    • H01L29/6653H01L21/28079H01L21/28097H01L29/495H01L29/665H01L29/66507H01L29/66545H01L29/6659
    • A method of making a MOS transistor is disclosed. The disclosed techniques can completely transform a polysilicon gate electrode into a metal silicide electrode through a brief thermal treatment process by extending the contact area between the polysilicide gate electrode and a metal layer prior to a formation of a metal silicide. The disclosed MOS transistor fabricating method comprises providing a semiconductor substrate further comprising a polysilicon gate electrode with a silicide layer thereon, a spacer, and source and drain regions with LDD regions; forming an insulating layer on the area of the substrate; polishing the insulating layer so that the top of the polysilicon gate electrode can be exposed; etching some part of the insulating layer and the spacer so that both lateral walls of the polysilicon gate electrode can be exposed; forming a metal layer on the substrate resulted from the preceding step so that the polysilicon gate electrode can be covered with the metal layer; and transforming completely the polysilicon gate electrode into a metal silicide gate electrode by performing a thermal treatment process.
    • 公开了制造MOS晶体管的方法。 所公开的技术可以通过短暂的热处理工艺将多晶硅栅极电极完全转变为金属硅化物电极,通过在形成金属硅化物之前延伸多硅化物栅极电极和金属层之间的接触面积。 所公开的MOS晶体管制造方法包括:提供半导体衬底,其还包括其上具有硅化物层的多晶硅栅极电极,间隔物以及具有LDD区域的源极和漏极区域; 在所述基板的区域上形成绝缘层; 抛光绝缘层,使得多晶硅栅电极的顶部可以被暴露; 蚀刻绝缘层和间隔物的一部分,使得可以暴露多晶硅栅电极的两个侧壁; 在上述步骤中形成在基板上的金属层,使得多晶硅栅极电极可被金属层覆盖; 并通过进行热处理工艺将多晶硅栅电极完全转变为金属硅化物栅电极。
    • 88. 发明申请
    • Method for forming inductor in semiconductor device
    • 在半导体器件中形成电感器的方法
    • US20050037589A1
    • 2005-02-17
    • US10876728
    • 2004-06-28
    • Young Kim
    • Young Kim
    • H01L27/02H01L21/02H01L27/08H01L21/8234
    • H01L28/10H01L27/08
    • The present invention relates to a method for manufacturing an inductor being a passive device in RE MEMS, RFCMOS, Bipolor/SiGe and BiCMOS semiconductor devices. According to the present invention, a first negative photoresist layer is covered on a substrate having a lower electrode. A via hole that will become a contact portion of the inductor is then defined by means of an exposure process using a first mask. A second negative photoresist layer is covered on the first negative photoresist layer. Trenches that will become line portions of the inductor are defined by an exposure process using a second mask. A damascene pattern having the via hole and the trenches is formed by means of a developing process and is then buried with copper, thus forming the inductor. Not only a thickness of the trenches in the line portion and a thickness of the via hole in the contact portion can be uniformly controlled, but also their height can be easily controlled. Therefore, that an inductor of a high quality can be manufactured.
    • 本发明涉及一种用于制造在RE MEMS,RFCMOS,双色/ SiGe和BiCMOS半导体器件中的无源器件的电感器的方法。 根据本发明,在具有下电极的基板上覆盖第一负光致抗蚀剂层。 然后将通过使用第一掩模的曝光处理来限定将成为电感器的接触部分的通孔。 第二负光致抗蚀剂层被覆盖在第一负光致抗蚀剂层上。 将成为电感线路部分的沟槽由使用第二掩模的曝光处理限定。 具有通孔和沟槽的镶嵌图案通过显影工艺形成,然后用铜掩埋,从而形成电感器。 不仅可以均匀地控制线部分中的沟槽的厚度和接触部分中的通孔的厚度,而且可以容易地控制其高度。 因此,可以制造高质量的电感器。