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81. 发明申请

US20120081345A1 Pixel Circuit And Display Device 有权
标题翻译：像素电路和显示设备
公开(公告)号：US20120081345A1
公开(公告)日：2012-04-05
申请号：US13376389
申请日：2010-06-07
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G3/3648 , G09G2300/0814 , G09G2300/0876 , G09G2330/021
摘要： A liquid crystal display device is provided which is capable of sufficiently decreasing power consumption in permanent display of still images while keeping high quality display in transparent mode, in high resolution display panels. In each pixel circuit, a pixel electrode is connected to a source line via a third transistor. When a refreshing circuit performs a refreshing operation, a boosting signal line is supplied with a voltage pulse. If the pixel electrode is at a high voltage level at this time point, a voltage at a node is boosted and a first transistor turns ON to supply a reference voltage to the pixel electrode as a refreshing voltage. If the pixel electrode is at a low voltage level, there is no boost, and the first transistor stays in OFF state, so a node assumes a voltage which is given by an off-resistance ratio of the first and the third transistors, and this voltage is supplied to the pixel electrode.
摘要翻译：提供了一种液晶显示装置，其能够在高分辨率显示面板中以透明模式保持高质量显示的同时，充分降低静止图像的永久显示中的功耗。在每个像素电路中，像素电极经由第三晶体管连接到源极线。当刷新电路进行刷新操作时，向升压信号线提供电压脉冲。如果在该时间点像素电极处于高电压电平，则节点处的电压被提升，并且第一晶体管导通以向像素电极提供参考电压作为刷新电压。如果像素电极处于低电压电平，则不存在升压，并且第一晶体管保持截止状态，因此节点呈现由第一和第三晶体管的截止电阻比给出的电压，并且这个电压被提供给像素电极。

82. 发明申请

US20110057242A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110057242A1
公开(公告)日：2011-03-10
申请号：US12935503
申请日：2009-03-31
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： H01L27/105
CPC分类号： H01L29/7885 , G11C16/0441 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825
摘要： A nonvolatile semiconductor memory device having a source-side-injected split-gate type of nonvolatile memory cell which can be formed by a one-layer polysilicon CMOS process is provided. A memory cell includes a first memory cell unit including first and second diffusion regions formed on a semiconductor substrate surface, and first and second gate electrodes separately formed through a gate insulation film on a first channel region between the first and second diffusion regions, a second memory cell unit including third and fourth diffusion regions formed on the semiconductor substrate surface, and a third gate electrode formed through a gate insulation film on a second channel region between the third and fourth diffusion regions, and a control terminal. The first to third gate electrodes are formed of the same electrode material layer. The second and third gate electrodes are electrically connected to form a floating gate capacitively coupled to the control terminal.
摘要翻译：提供一种具有源极侧注入的分离栅极型非易失性存储单元的非易失性半导体存储器件，其可通过单层多晶硅CMOS工艺形成。存储单元包括：第一存储单元单元，包括形成在半导体衬底表面上的第一和第二扩散区;以及第一和第二栅电极，分别形成在第一和第二扩散区之间的第一沟道区上的栅极绝缘膜; 存储单元单元，包括形成在所述半导体衬底表面上的第三和第四扩散区;以及第三栅电极，通过栅极绝缘膜形成在第三和第四扩散区之间的第二沟道区上，以及控制端。第一至第三栅电极由相同的电极材料层形成。第二和第三栅电极电连接以形成电容耦合到控制端的浮栅。

83. 发明授权

US07151693B2 Method of writing data to a non-volatile semiconductor memory 有权
标题翻译：将数据写入非易失性半导体存储器的方法
公开(公告)号：US07151693B2
公开(公告)日：2006-12-19
申请号：US11101415
申请日：2005-04-08
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/0491 , G11C16/10 , G11C16/3418
摘要： A method of writing data into a non-volatile semiconductor memory having a plurality of memory cells in which a word line is shared by memory cells and a bit line is shared by adjacent memory cells, the method including writing the data into memory cells connected to the same word line sequentially from a memory cell at one end to a memory cell at another end.
摘要翻译：一种将数据写入非易失性半导体存储器的方法，所述非易失性半导体存储器具有多个存储器单元，其中字线由存储器单元共享并且位线由相邻存储器单元共享，所述方法包括将数据写入连接到相同的字线顺序地从一端的存储器单元到另一端的存储器单元。

84. 发明授权

US07057944B2 Semiconductor readout circuit 失效
标题翻译：半导体读出电路
公开(公告)号：US07057944B2
公开(公告)日：2006-06-06
申请号：US11013119
申请日：2004-12-14
申请人： Nobuhiko Ito , Kaoru Yamamoto , Yoshimitsu Yamauchi
发明人： Nobuhiko Ito , Kaoru Yamamoto , Yoshimitsu Yamauchi
IPC分类号： G11C7/06
CPC分类号： G11C7/1069 , G11C7/062 , G11C7/1051 , G11C7/12
摘要： A semiconductor readout circuit reads out a potential of each of plural data lines by comparing the potential with a potential of a common reference data line, using a sense amplifier provided for each of the data lines. This semiconductor readout circuit has a current control circuit provided for each of the data lines. The current control circuit controls the potential of the corresponding one of the data lines so that a potential difference between the potential of the corresponding data line and the potential of the reference data line can be reduced based on an output as to the potential difference detected by the sense amplifier.
摘要翻译：半导体读出电路通过使用为每条数据线提供的读出放大器来比较电位与公共参考数据线的电位，来读出多条数据线中的每一条线的电位。该半导体读出电路具有为每条数据线设置的电流控制电路。电流控制电路控制对应的一条数据线的电位，使得相应的数据线的电位与参考数据线的电位之间的电位差可以基于关于由读出放大器。

85. 发明申请

US20060002175A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060002175A1
公开(公告)日：2006-01-05
申请号：US11173925
申请日：2005-07-01
申请人： Kaoru Yamamoto , Nobuhiko Ito , Yoshimitsu Yamauchi
发明人： Kaoru Yamamoto , Nobuhiko Ito , Yoshimitsu Yamauchi
IPC分类号： G11C11/24
CPC分类号： G11C16/26 , G11C16/0491 , G11C16/24
摘要： A semiconductor memory device having a virtual ground line type memory array structure includes a readout circuit for selecting a pair of selected bit lines connected to the source and the drain of a memory cell to be read, applying a predetermined voltage to between the paired selected bit lines, and sensing a memory cell current flowing through the memory cell to be read, and a counter potential generation circuit for generating from an intermediate node potential, which is higher than any level of the potential on the selected bit lines and supplied from an intermediate node on a current path for feeding the memory cell current in the readout circuit, a counter potential which varies in the same direction as of the intermediate node potential depending on the memory cell current so that its variation is greater than that of the intermediate node potential, wherein the counter potential is applied to an unselected bit line allocated next to one at a high level of the paired selected bit lines.
摘要翻译：具有虚拟接地线型存储器阵列结构的半导体存储器件包括读出电路，用于选择连接到要读取的存储单元的源极和漏极的一对选定位线，将预定电压施加在成对选定位之间并且感测流过待读取的存储单元的存储单元电流，以及用于从中间节点电位产生的逆电位产生电路，该中间节点电位高于所选位线上的电位的任何电平，并从中间层在电流路径上用于馈送读出电路中的存储单元电流的一个节点，根据存储单元电流使与中间节点电位相同的方向变化的反电位，使得其变化大于中间节点电位的变化，其中所述计数器电位被施加到在所选择的所述配对的高电平处的一个旁边分配的未选位线位线。

86. 发明授权

US06952031B2 Nonvolatile semiconductor memory and method of operating the same 有权
公开(公告)号：US06952031B2
公开(公告)日：2005-10-04
申请号：US10314021
申请日：2002-12-09
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G11C16/04 , G11C7/00 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/112 , H01L27/115 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115
摘要： A nonvolatile semiconductor memory having a memory cell comprises: a semiconductor substrate having a pair of trenches formed on a surface thereof; first electrodes formed in a pair of trenches through the intervention of a first insulating film, respectively; a second electrode formed on the semiconductor substrate between the trenches through the intervention of a second insulating film; and a third electrode formed on the second electrode through the intervention of a third insulating film.

87. 发明授权

US06531732B2 Nonvolatile semiconductor memory device, process of manufacturing the same and method of operating the same 有权
公开(公告)号：US06531732B2
公开(公告)日：2003-03-11
申请号：US09897434
申请日：2001-07-03
申请人： Yasuhiro Sugita , Yoshimitsu Yamauchi
发明人： Yasuhiro Sugita , Yoshimitsu Yamauchi
IPC分类号： H01L29788
CPC分类号： H01L27/11568 , G11C16/0475 , H01L27/115
摘要： A nonvolatile semiconductor memory device comprises: a pair of impurity diffusion layers formed on a surface of a semiconductor substrate; two control gates formed on the semiconductor substrate through the intervention of a charge accumulating layer, the two control gates being provided between the pair of impurity diffusion layers and adjacent to each of the impurity diffusion layers; a word gate transistor including a word line formed on the semiconductor substrate through the intervention of a word gate insulating film between the control gates, wherein the two control gates and the word gate transistor are connected in series to form a unit cell.

88. 发明授权

US5510284A Method for manufacturing an asymetric non-volatile memory 失效
标题翻译：非对称非易失性存储器的制造方法
公开(公告)号：US5510284A
公开(公告)日：1996-04-23
申请号：US508132
申请日：1995-07-27
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517
摘要： A method for manufacturing a non-volatile memory comprising the steps of:(i) forming a first electrode on a semiconductor substrate having a first insulating film;(ii) implanting impurity ions to an area adjacent to one side of the first electrode while masking at least an area adjacent to another side of the first electrode;(iii) forming a second insulating film on the semiconductor substrate including the first electrode, followed by depositing a conductive film on the entire surface of the second insulating film;(iv) implanting impurity ions into the semiconductor substrate via the conductive film; and(v) patterning the conductive film to constitute a second electrode.
摘要翻译：一种制造非易失性存储器的方法，包括以下步骤：（i）在具有第一绝缘膜的半导体衬底上形成第一电极; （ii）将杂质离子注入到与所述第一电极的一侧相邻的区域中，同时掩蔽至少与所述第一电极的另一侧相邻的区域; （iii）在包括第一电极的半导体衬底上形成第二绝缘膜，然后在第二绝缘膜的整个表面上沉积导电膜; （iv）经由导电膜将杂质离子注入到半导体衬底中; 和（v）图案化导电膜以构成第二电极。

89. 发明授权

US5411904A Process for fabricating nonvolatile random access memory having a tunnel oxide film 失效
标题翻译：制造具有隧道氧化膜的非挥发性随机存取存储器的方法
公开(公告)号：US5411904A
公开(公告)日：1995-05-02
申请号：US231740
申请日：1994-04-25
申请人： Yoshimitsu Yamauchi , Kenichi Tanaka , Keizo Sakiyama , Akitsu Ayukawa
发明人： Yoshimitsu Yamauchi , Kenichi Tanaka , Keizo Sakiyama , Akitsu Ayukawa
IPC分类号： H01L21/8247 , H01L21/266
CPC分类号： H01L27/11521 , H01L27/11524 , Y10S438/981
摘要： A nonvolatile random access memory comprising a nonvolatile random access memory unit having on a substrate an EEPROM having a tunnel oxide film and a floating gate, and a DRAM linked to the EEPROM, a thermal oxide film being selectively formed between the EEPROM and another EEPROM adjacent thereto, the tunnel regions of the respective EEPROMs being provided as self-aligned with the respective ends of the thermal oxide film and positioned at the respective ends of an impurity ion implantation pattern for use in forming a source region of the EEPROMs.
摘要翻译：一种非易失性随机存取存储器，包括在衬底上具有隧道氧化物膜和浮动栅极的EEPROM和与EEPROM连接的DRAM的非易失性随机存取存储器单元，选择性地形成在EEPROM和另一个EEPROM之间的热氧化膜各个EEPROM的隧道区域被设置为与热氧化膜的相应端部自对准并且位于用于形成EEPROM的源极区域的杂质离子注入图案的各个端部。

90. 发明授权

US5400280A Nonvolatile memory and a method of writing data thereto 失效
标题翻译：非易失性存储器和向其写入数据的方法
公开(公告)号：US5400280A
公开(公告)日：1995-03-21
申请号：US89330
申请日：1993-07-12
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C16/0483
摘要： The present invention provides a nonvolatile memory and a method of writing data thereto. The nonvolatile memory includes a memory cell having a semiconductor substrate, a first electrode on the substrate formed through the intermediary of an insulating film, a floating gate adjacent to the first electrode formed through the intermediary of an insulating film, and a second electrode deposited at least on the floating gate through the intermediary of an insulating film, wherein a plurality of the memory cells are arranged in the directions of X and Y to form a matrix, at least 2 memory cells arranged in the direction of X form a memory cell group, a single first impurity diffused layer and a single second impurity diffused layer used in common in the respective cells are formed at the both ends of the memory cell group, and the first electrode and the second electrode of the plurality of memory cells arranged in the direction of Y are connected in common.
摘要翻译：本发明提供一种非易失性存储器以及向其写入数据的方法。非易失性存储器包括具有半导体衬底的存储单元，通过绝缘膜形成的衬底上的第一电极，与通过绝缘膜形成的第一电极相邻的浮置栅极和沉积在第一电极上的第二电极至少在浮动栅极上通过绝缘膜的介质，其中多个存储单元沿X和Y的方向排列以形成矩阵，沿着X方向布置的至少2个存储单元形成存储单元组在存储单元组的两端形成单个第一杂质扩散层和单个第二杂质扩散层，共同使用的单个第二杂质扩散层，并且多个存储单元中的第一电极和第二电极布置在 Y的方向共同连接。

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