专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07790513B2 Substrate based unmolded package 有权
标题翻译：基于底物的未模塑包装
公开(公告)号：US07790513B2
公开(公告)日：2010-09-07
申请号：US12358654
申请日：2009-01-23
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L21/00
CPC分类号： H01L23/49861 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/48091 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/45147
摘要： A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.
摘要翻译：公开了一种半导体管芯封装。在一个实施例中，半导体管芯封装具有衬底。它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附接区域和具有引线表面的引线，以及（ii）模制材料。裸片附着表面和引线表面通过模制材料暴露。半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。

82. 发明授权

US07618896B2 Semiconductor die package including multiple dies and a common node structure 有权
标题翻译：半导体管芯封装包括多个管芯和一个共同的节点结构
公开(公告)号：US07618896B2
公开(公告)日：2009-11-17
申请号：US11410504
申请日：2006-04-24
申请人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
发明人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
IPC分类号： H01L23/34
CPC分类号： H01L23/49575 , H01L23/492 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.
摘要翻译：公开了一种能够安装在母板上的半导体管芯封装。半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

83. 发明申请

US20090230540A1 HIGH PERFORMANCE MULTI-CHIP FLIP CHIP PACKAGE 失效
标题翻译：高性能多芯片卷芯片包装
公开(公告)号：US20090230540A1
公开(公告)日：2009-09-17
申请号：US12407532
申请日：2009-03-19
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： B23K1/0008 , B23K3/0623 , B23K2101/40 , H01L23/492 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.
摘要翻译：一种用于改进的多芯片半导体封装的结构和方法，其将封装电阻降低到可忽略的水平，并提供优异的热性能。通过提供电绝缘的引线框架来促进多个管芯的外壳，该引线框架通过层压材料的非导电层与共同的基底载体分开。在每个引线框架中形成的腔内部附着有硅管芯。然后通过分布在每个管芯的表面以及与每个管芯相邻的引线框架的边缘的焊料凸块阵列来制造硅片的有源表面与印刷电路板的直接连接。

84. 发明申请

US20080105957A1 THIN, THERMALLY ENHANCED FLIP CHIP IN A LEADED MOLDED PACKAGE 有权
标题翻译：薄膜，热成型包装中的热成型芯片
公开(公告)号：US20080105957A1
公开(公告)日：2008-05-08
申请号：US11961589
申请日：2007-12-20
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L23/495
CPC分类号： H01L23/495 , H01L23/49548 , H01L23/49555 , H01L23/49562 , H01L23/49568 , H01L24/34 , H01L24/37 , H01L2224/16 , H01L2224/16245 , H01L2224/37599 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/37099
摘要： Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.
摘要翻译：本发明的实施例涉及半导体管芯封装。本发明的一个实施例涉及一种半导体管芯封装，其包括：（a）包括第一表面和第二表面的半导体管芯，（b）源极引线结构，其包括具有主表面的突出区域，所述源极引线结构被耦合（c）栅极引线结构，其耦合到所述第一表面，以及（d）围绕所述源极引线结构和所述半导体管芯的模制材料，其中所述模制材料暴露所述半导体管芯的所述第二表面，以及源极引线结构的主表面。

85. 发明授权

US07335532B2 Method of assembly for multi-flip chip on lead frame on overmolded IC package 失效
标题翻译：包覆成型IC封装上引线框架上多重倒装芯片的组装方法
公开(公告)号：US07335532B2
公开(公告)日：2008-02-26
申请号：US11560935
申请日：2006-11-17
申请人： Jonathan A. Noquil , Seung Yong Choi , Rajeev Joshi , Chung-Lin Wu
发明人： Jonathan A. Noquil , Seung Yong Choi , Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L21/44
CPC分类号： H01L25/16 , H01L23/3128 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.
摘要翻译：多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。

86. 发明授权

US07271497B2 Dual metal stud bumping for flip chip applications 有权
标题翻译：双金属螺柱凸块用于倒装芯片应用
公开(公告)号：US07271497B2
公开(公告)日：2007-09-18
申请号：US10386211
申请日：2003-03-10
申请人： Rajeev Joshi , Consuelo Tangpuz , Margie T. Rios , Erwin Victor R. Cruz
发明人： Rajeev Joshi , Consuelo Tangpuz , Margie T. Rios , Erwin Victor R. Cruz
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L24/81 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/11 , H01L2224/1134 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2224/16 , H01L2224/81192 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2224/29099 , H01L2924/00 , H01L2224/05655 , H01L2924/00014 , H01L2224/05666 , H01L2224/05124
摘要： A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.
摘要翻译：公开了一种用于形成螺柱凸起的半导体管芯的方法。该方法包括在穿过毛细管中的孔的涂覆线的尖端处形成球，其中涂覆线具有芯和抗氧化涂层。将形成的球按压到半导体管芯上的导电区域。涂覆的线材被切割，从而在导电区域上留下导电柱状凸块，其中导电柱形凸块包括内部导电部分和外部抗氧化层。

87. 发明申请

US20060284291A1 Lead frame structure with aperture or groove for flip chip in a leaded molded package 失效
公开(公告)号：US20060284291A1
公开(公告)日：2006-12-21
申请号：US11448962
申请日：2006-06-06
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L24/40 , H01L21/565 , H01L23/49503 , H01L23/49548 , H01L23/49562 , H01L24/37 , H01L24/81 , H01L2224/16 , H01L2224/16245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/81801 , H01L2224/83801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/37099
摘要： A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

88. 发明申请

US20060189116A1 Dual metal stud bumping for flip chip applications 有权
公开(公告)号：US20060189116A1
公开(公告)日：2006-08-24
申请号：US11404650
申请日：2006-04-14
申请人： Rajeev Joshi , Consuelo Tangpuz , Margie Rios , Erwin Victor Cruz
发明人： Rajeev Joshi , Consuelo Tangpuz , Margie Rios , Erwin Victor Cruz
IPC分类号： H01L21/44
CPC分类号： H01L24/81 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/11 , H01L2224/1134 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2224/16 , H01L2224/81192 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2224/29099 , H01L2924/00 , H01L2224/05655 , H01L2924/00014 , H01L2224/05666 , H01L2224/05124
摘要： A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

89. 发明申请

US20060151861A1 Method to manufacture a universal footprint for a package with exposed chip 失效
标题翻译：制造具有裸露芯片的封装的通用尺寸的方法
公开(公告)号：US20060151861A1
公开(公告)日：2006-07-13
申请号：US11035918
申请日：2005-01-13
申请人： Jonathan Noquil , Connie Tangpuz , Romel Manatad , Stephen Martin , Rajeev Joshi , Venkat Iyer
发明人： Jonathan Noquil , Connie Tangpuz , Romel Manatad , Stephen Martin , Rajeev Joshi , Venkat Iyer
IPC分类号： H01L23/495
CPC分类号： H01L23/36 , H01L23/488 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H05K3/341 , H05K2201/09681 , H05K2201/10166 , H05K2201/10477 , H05K2201/10689 , H05K2201/10969 , Y02P70/613 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.
摘要翻译：公开了一种半导体管芯封装。它可以包括具有第一表面和第二表面的半导体管芯和引线框架结构。模制材料可以围绕模具的至少一部分和引线框架结构的至少一部分形成。可焊层可以在模制材料的外表面和半导体管芯的第一表面上。

90. 发明授权

US07061077B2 Substrate based unmolded package including lead frame structure and semiconductor die 有权
标题翻译：基于基板的未模制封装，包括引线框架结构和半导体管芯
公开(公告)号：US07061077B2
公开(公告)日：2006-06-13
申请号：US10233248
申请日：2002-08-30
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H01L23/495
CPC分类号： H01L23/49861 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/48091 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/45147
摘要： A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.
摘要翻译：公开了一种半导体管芯封装。在一个实施例中，半导体管芯封装具有衬底。它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附接区域和具有引线表面的引线，以及（ii）模制材料。裸片附着表面和引线表面通过模制材料暴露。半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式