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81. 发明授权

US08247788B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08247788B2
公开(公告)日：2012-08-21
申请号：US12659175
申请日：2010-02-26
申请人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
发明人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
IPC分类号： H01L45/00
CPC分类号： H01L27/2445 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147
摘要： The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.
摘要翻译：非易失性存储器件包括至少一对第一电极线，设置在至少一对第一电极线之间的至少一个器件结构和设置在该至少一个器件结构与至少一对第一电极线之间的电介质层电极线。所述至少一个器件结构包括第二电极线，所述第二电极线包括第一导电类型半导体，与所述第二电极线相邻的电阻改变材料层，与所述电阻变化材料层相邻的通道，并且包括不同于所述第一导电类型的第一导电型半导体导电型半导体和与沟道相邻的第三电极线，并且包括第一导电型半导体。

82. 发明授权

US08148767B2 Semiconductor memory devices including recess-type control gate electrodes and methods of fabricating the semiconductor memory devices 失效
标题翻译：包括凹型控制栅电极的半导体存储器件和制造半导体存储器件的方法
公开(公告)号：US08148767B2
公开(公告)日：2012-04-03
申请号：US11709860
申请日：2007-02-23
申请人： Yoon-dong Park , June-mo Koo , Kyoung-lae Cho
发明人： Yoon-dong Park , June-mo Koo , Kyoung-lae Cho
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： A semiconductor memory device includes a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer interposed between a sidewall of the control gate electrode and the semiconductor substrate, a tunneling insulation layer interposed between the storage node layer and the semiconductor substrate, a blocking insulation layer interposed between the storage node layer and the control gate electrode, and first and second channel regions formed around a surface of the semiconductor substrate to at least partially surround the control gate electrode. The semiconductor memory device may include a plurality of control gate electrodes, storage node layers, tunneling insulation layers, blocking insulation layers, and continuous first and second channel regions. A method of fabricating the semiconductor memory device includes etching the semiconductor substrate to form a plurality of holes, forming the tunneling insulation layers, storage node layers, blocking insulation layers, and control gate electrodes.
摘要翻译：半导体存储器件包括半导体衬底，凹入半导体衬底中的控制栅极电极，插在控制栅电极的侧壁和半导体衬底之间的存储节点层，介于存储节点层和半导体衬底之间的隧道绝缘层衬底，介于存储节点层和控制栅电极之间的阻挡绝缘层，以及形成在半导体衬底的表面周围以至少部分地围绕控制栅电极的第一和第二沟道区。半导体存储器件可以包括多个控制栅电极，存储节点层，隧道绝缘层，阻挡绝缘层以及连续的第一和第二沟道区。制造半导体存储器件的方法包括蚀刻半导体衬底以形成多个孔，形成隧道绝缘层，存储节点层，阻挡绝缘层和控制栅电极。

83. 发明授权

US08050087B2 Non-volatile memory device including block state confirmation cell and method of operating the same 有权
标题翻译：包括块状态确认单元的非易失性存储器件及其操作方法
公开(公告)号：US08050087B2
公开(公告)日：2011-11-01
申请号：US12071349
申请日：2008-02-20
申请人： Ju-hee Park , Jae-woong Hyun , Kyoung-lae Cho , Yoon-dong Park , Seung-hoon Lee , Kee-won Kwon
发明人： Ju-hee Park , Jae-woong Hyun , Kyoung-lae Cho , Yoon-dong Park , Seung-hoon Lee , Kee-won Kwon
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G11C2211/5641 , G11C2211/5646
摘要： Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.
摘要翻译：提供了具有块状态确认单元的半导体器件，其可以存储指示写入多个存储器单元的数据位数的信息，基于写入的数据位的数量读取存储器数据的方法和/或存储器存储指示写入数据位数的信息的编程方法。半导体器件可以包括一个或多个存储器块和控制器。每个存储器块可以包括存储数据的多个存储单元，以及存储指示写入存储单元的数据位数的信息的块状态确认单元。控制器可以基于在块状态确认单元中的信息中指示的数据位数来从存储器块读取数据位。

84. 发明授权

US07910909B2 Non-volatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07910909B2
公开(公告)日：2011-03-22
申请号：US12232745
申请日：2008-09-23
申请人： Suk-pil Kim , Yoon-dong Park , June-mo Koo
发明人： Suk-pil Kim , Yoon-dong Park , June-mo Koo
IPC分类号： H01L45/00
CPC分类号： H01L27/249 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer.
摘要翻译：提供了可以被配置为堆叠结构并且可以更容易地高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。提供至少一个第一电极和至少一个第二电极。所述至少一个第二电极可以穿过所述至少一个第一电极。至少一个数据存储层可以在至少一个第一电极和至少一个第二电极之间的交叉点处。所述至少一个第一电极和所述至少一个第二电极中的任何一个可以包括连接到所述至少一个数据存储层的至少一个结二极管。

85. 发明授权

US07885107B2 Methods of programming non-volatile memory cells 有权
标题翻译：编程非易失性存储单元的方法
公开(公告)号：US07885107B2
公开(公告)日：2011-02-08
申请号：US12219663
申请日：2008-07-25
申请人： Ju-hee Park , Young-moon Kim , Yoon-dong Park , Seung-hoon Lee , Kyoung-lae Cho , Sung-jae Byun , Seung-hwan Song
发明人： Ju-hee Park , Young-moon Kim , Yoon-dong Park , Seung-hoon Lee , Kyoung-lae Cho , Sung-jae Byun , Seung-hwan Song
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621 , G11C2211/5648
摘要： A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit.
摘要翻译：一种编程非易失性存储单元的方法包括通过将非易失性存储单元的阈值电压设置为多个阈值电压分布中的第一个内的第一电压电平来对第一位多位数据进行编程。通过基于第二位的值将阈值电压设置为第二电压电平来编程多位数据的第二位。如果第二位是第二值，则第二电压电平与第一电压电平相同，如果第二位是第二值，则第二电压电平在多个阈值电压分布的一秒内。通过将阈值电压设置为基于第三位的值的第三电压电平来编程多位数据的第三位。

86. 发明申请

US20100073462A1 Three dimensional image sensor 有权
标题翻译：三维图像传感器
公开(公告)号：US20100073462A1
公开(公告)日：2010-03-25
申请号：US12585745
申请日：2009-09-23
申请人： Seung-hoon Lee , Eric R. Fossum , Yoon-dong Park , Kyoung-lae Cho , Sung-jae Byun
发明人： Seung-hoon Lee , Eric R. Fossum , Yoon-dong Park , Kyoung-lae Cho , Sung-jae Byun
IPC分类号： H04N13/02
CPC分类号： H04N5/3696 , H04N5/347 , H04N13/25
摘要： A three-dimensional (3D) image sensor includes a plurality of color pixels, and a plurality of distance measuring pixels. Where the plurality of color pixels and the plurality of distance measuring pixels are arranged in an array, and a group of distance measuring pixels, from among the plurality of distance measuring pixels, are disposed so that a corner of each distance measuring pixel in the group of distance-measuring pixels is adjacent to a corner of an adjacent distance-measuring pixel in the group of distance-measuring pixels. The group of distance measuring pixels is capable of jointly outputting one distance measurement signal.
摘要翻译：三维（3D）图像传感器包括多个彩色像素和多个距离测量像素。在多个彩色像素和多个距离测量像素排列成阵列的情况下，并且从多个距离测量像素之中设置一组距离测量像素，使得组中的每个距离测量像素的角部距离测量像素的距离测量像素组中的相邻距离测量像素的角部相邻。距离测量像素组能够共同输出一个距离测量信号。

87. 发明申请

US20100044778A1 Non-volatile memory device and method of manufacturing same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20100044778A1
公开(公告)日：2010-02-25
申请号：US12461416
申请日：2009-08-11
申请人： Kwang-soo Seol , Yoon-dong Park
发明人： Kwang-soo Seol , Yoon-dong Park
IPC分类号： H01L29/792 , H01L21/20 , H01L21/28
CPC分类号： H01L27/11578 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A non-volatile memory device and a method of manufacturing the non-volatile memory device are provided. At least one first semiconductor layer and at least one second semiconductor layer are disposed. At least one control gate electrode is disposed between the at least one first semiconductor layer and the at least one second semiconductor layer. At least one first layer selection line is capacitively coupled to the at least one first semiconductor layer. At least one second layer selection line is capacitively coupled to the at least one second semiconductor layer.
摘要翻译：提供了一种非易失性存储器件和制造该非易失性存储器件的方法。设置至少一个第一半导体层和至少一个第二半导体层。至少一个控制栅电极设置在至少一个第一半导体层和至少一个第二半导体层之间。至少一个第一层选择线电容耦合到至少一个第一半导体层。至少一个第二层选择线电容耦合到至少一个第二半导体层。

88. 发明申请

US20090294633A1 Image sensor using photo-detecting molecule and method of operating the same 有权
标题翻译：使用光检测分子的图像传感器及其操作方法
公开(公告)号：US20090294633A1
公开(公告)日：2009-12-03
申请号：US12385122
申请日：2009-03-31
申请人： Kwang-soo Seol , Yoon-dong Park
发明人： Kwang-soo Seol , Yoon-dong Park
IPC分类号： H01L27/146 , H01L31/0256 , H01L51/46
CPC分类号： H01L27/14603 , H01L27/14627 , H01L27/307 , H01L51/0043 , H01L51/0073 , H01L51/424 , H01L51/4246 , Y02E10/549
摘要： Provided is an image sensor using a photo-detecting molecule and a method of operating the image sensor. The image sensor may include a plurality of first electrodes disposed parallel to each other and a plurality of second electrodes disposed parallel to each other in a direction perpendicular to the first electrodes and above the first electrodes, and a plurality of subpixels formed in regions where the first electrodes cross the second electrodes. Each of the subpixels may comprise a photo-detecting molecule layer that may generate charges by absorbing light having a certain wavelength, a charge generation layer that may form a plurality of secondary electrons by receiving the charges from the photo-detecting molecule layer when a known voltage is applied between the first electrodes and the second electrodes, and a variable resistance layer, an electrical state of which is changed by receiving the secondary electrons generated from the charge generation layer.
摘要翻译：提供了使用光检测分子的图像传感器和操作图像传感器的方法。图像传感器可以包括彼此平行设置的多个第一电极和在垂直于第一电极并且在第一电极上方彼此平行设置的多个第二电极，以及多个子像素，其形成在第一电极与第二电极交叉。每个子像素可以包括可以通过吸收具有一定波长的光而产生电荷的光检测分子层，电荷产生层可以通过从已知的光检测分子层接收电荷而形成多个二次电子在第一电极和第二电极之间施加电压，并且通过接收从电荷产生层产生的二次电子而改变其电状态的可变电阻层。

89. 发明授权

US07585755B2 Method of fabricating non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07585755B2
公开(公告)日：2009-09-08
申请号：US11978567
申请日：2007-10-30
申请人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
发明人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
IPC分类号： H01L21/8239 , H01L29/788 , H01L29/792 , H01L27/105
CPC分类号： H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.
摘要翻译：根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。多个下电荷存储层可以形成在半导体层的底表面上。可以在多个下电荷存储层上形成多个下控制栅电极。多个上电荷存储层可以形成在半导体层的顶表面上。多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

90. 发明授权

US07577042B2 Method of programming multi-level semiconductor memory device and multi-level semiconductor memory device 有权
标题翻译：编程多电平半导体存储器件和多电平半导体存储器件的方法
公开(公告)号：US07577042B2
公开(公告)日：2009-08-18
申请号：US11978578
申请日：2007-10-30
申请人： Jae-woong Hyun , Kyoung-lae Cho , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee , Sung-jae Byun
发明人： Jae-woong Hyun , Kyoung-lae Cho , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee , Sung-jae Byun
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5642
摘要： Provided in one example embodiment, a method of programming n bits of data to a semiconductor memory device may include outputting a first bit of data written in a memory cell from a first latch, storing the first bit of the data to a third latch, storing a second bit of the data to the first latch, outputting the second bit of the data from the first latch, storing the second bit of the data to the second latch, and writing the second bit of the data stored in the second latch to the memory cell with reference to a data storage state of the first bit of the data stored in the third latch.
摘要翻译：在一个示例性实施例中提供了一种将半位数据数据编程到半导体存储器件的方法可以包括从第一锁存器输出写入存储器单元中的第一位数据，将第一位数据存储到第三锁存器，存储将数据的第二位输出到第一锁存器，从第一锁存器输出数据的第二位，将数据的第二位存储到第二锁存器，以及将存储在第二锁存器中的数据的第二位写入到参考存储在第三锁存器中的数据的第一位的数据存储状态的存储器单元。

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