专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06965299B1 High-speed, low-power crossbar switch 失效
标题翻译：高速，低功率交叉开关
公开(公告)号：US06965299B1
公开(公告)日：2005-11-15
申请号：US09625802
申请日：2000-07-26
申请人： William J. Dally , Daniel K. Hartman
发明人： William J. Dally , Daniel K. Hartman
IPC分类号： G06F13/40 , H04L12/50
CPC分类号： G06F13/4009
摘要： In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.
摘要翻译：在交叉点开关中，输入总线和输出总线均以低摆幅驱动。自定时，差分，推挽，低回转驱动电路驱动输入总线，并在交叉点提供驱动输出总线。在数据总线的交叉点和输出端提供了时钟的再生感测放大器。

82. 发明授权

US06614268B2 High-speed, low-power inter-chip transmission system 有权
标题翻译：高速，低功耗的片内传输系统
公开(公告)号：US06614268B2
公开(公告)日：2003-09-02
申请号：US10172535
申请日：2002-06-13
申请人： William J. Dally , Daniel K. Hartman
发明人： William J. Dally , Daniel K. Hartman
IPC分类号： G01R1900
CPC分类号： G11C7/1084 , G11C7/1006 , G11C7/1051 , G11C7/1066 , G11C7/1078
摘要： In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.
摘要翻译：在集成电路中，数据链路依赖于低摆幅差分信号。推挽式驱动器电路和接收器电路均由公共片上时钟计时。驱动器电路包括NMOS晶体管的H桥和减少电路的功率需求的线间预充电电路。链路内的时钟中继器本身可以包括时钟接收器和具有线间预充电的H桥驱动器。

83. 发明授权

US06606656B2 Apparatus and methods for connecting modules using remote switching 有权
公开(公告)号：US06606656B2
公开(公告)日：2003-08-12
申请号：US09765138
申请日：2001-01-18
申请人： Philip P. Carvey , William J. Dally , Larry R. Dennison
发明人： Philip P. Carvey , William J. Dally , Larry R. Dennison
IPC分类号： G06F15177
CPC分类号： G06F15/17343 , G06F15/8023
摘要： A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set. Each configuration controller operates as a remotely configurable switch that configures a topology formed by the backplanes and the module connectors. In particular, by adding a single module, the topology can be expanded incrementally.

84. 发明授权

US06205532B1 Apparatus and methods for connecting modules using remote switching 失效
标题翻译：使用远程开关连接模块的装置和方法
公开(公告)号：US06205532B1
公开(公告)日：2001-03-20
申请号：US09083722
申请日：1998-05-22
申请人： Philip P. Carvey , William J. Dally , Larry R. Dennison
发明人： Philip P. Carvey , William J. Dally , Larry R. Dennison
IPC分类号： G06F902
CPC分类号： G06F15/17343 , G06F15/8023
摘要： A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set. Each configuration controller operates as a remotely configurable switch that configures a topology formed by the backplanes and the module connectors. In particular, by adding a single module, the topology can be expanded incrementally.
摘要翻译：模块连接组件连接可以远程更改的环面配置中的模块。特别地，通过从提供终端电路径的导电路径远程切换到提供穿越电路径的导电路径，可以将单个模块添加到或从配置中删除。该组件包括两个背板，用于将模块电连接到一个背板的第一组模块连接器，以及用于将模块电连接到另一背板的第二组模块连接器。组件还包括配置控制器。每个配置控制器在将第一组的多个模块连接器彼此电连接的末端电路之间进行选择，以及将第一组的模块连接器电连接到第二组的模块连接器的直通电路径。每个配置控制器都可以作为远程配置开关，用于配置由背板和模块连接器形成的拓扑。特别地，通过添加单个模块，可以逐渐扩展拓扑。

85. 发明授权

US09025456B2 Speculative reservation for routing networks 有权
标题翻译：路由网络的推测预留
公开(公告)号：US09025456B2
公开(公告)日：2015-05-05
申请号：US13402476
申请日：2012-02-22
申请人： Nan Jiang , William J. Dally
发明人： Nan Jiang , William J. Dally
IPC分类号： H04L1/00 , G06F15/16 , H04L12/801 , H04L12/913 , H04L12/911
CPC分类号： H04L47/12 , H04L47/724 , H04L47/822
摘要： Aspects relate to methods, devices and manufacturing relating to routing networks including a method for routing data units. The data units are individually routable through a routing network. A reservation request data unit is received over the routing network and from a sender. At least one speculative data unit associated with the reservation request data unit from the sender is received. The at least one speculative data unit is dropped in response to the at least one speculative data unit being blocked within the routing network. The sender is provided, over the routing network, a negative acknowledgement data unit that indicates the dropping of the at least one speculative data unit. The sender is provided a grant data unit indicating a start time. After the start time, at least one non-speculative data unit corresponding to the reservation request from the sender is received.
摘要翻译：方面涉及与路由网络有关的方法，设备和制造，包括路由数据单元的方法。数据单元可以通过路由网络单独路由。通过路由网络和发送方接收预约请求数据单元。接收到与来自发送者的预约请求数据单元相关联的至少一个推测数据单元。所述至少一个推测数据单元响应于所述至少一个推测数据单元在所述路由网络内被阻塞而被丢弃。发送方通过路由网络提供指示丢弃至少一个推测数据单元的否定确认数据单元。向发送者提供指示开始时间的授权数据单元。在开始时间之后，接收与来自发送者的预约请求对应的至少一个非推测数据单元。

86. 发明授权

US08681837B2 Digital Transmitter 有权
标题翻译：数字发射机
公开(公告)号：US08681837B2
公开(公告)日：2014-03-25
申请号：US12942607
申请日：2010-11-09
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04B1/38 , H03H7/40 , H04L27/01 , H04L23/00
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer as logic level sequences are transmitted at different frequencies.
摘要翻译：提供在数字发射机中的均衡器补偿信号到数字接收机的信号衰减。均衡器产生信号电平作为位历史的逻辑功能，以强调相对于重复信号电平的转换信号电平。优选的均衡器包括使用查找表的FIR转换滤波器。包括FIR滤波器和数模转换器的并行电路为低速电路提供高速均衡器。均衡器特别适用于柜内和局域网传输，其中反馈电路有助于均衡器的自适应训练，因为逻辑电平序列以不同的频率传输。

87. 发明授权

US08311147B2 Digital transmitter 有权
公开(公告)号：US08311147B2
公开(公告)日：2012-11-13
申请号：US13091382
申请日：2011-04-21
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L27/04 , H04L25/03 , H04L27/00 , H03K5/156
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

88. 发明申请

US20120274377A1 SINGLE-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT 有权
标题翻译：单触发低能量FLIP-FLOP电路
公开(公告)号：US20120274377A1
公开(公告)日：2012-11-01
申请号：US13095641
申请日：2011-04-27
申请人： Jonah M. Alben , William J. Dally
发明人： Jonah M. Alben , William J. Dally
IPC分类号： H03K3/286
CPC分类号： H03K3/286 , H03K3/012 , H03K3/356139 , H03K3/356191
摘要： One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
摘要翻译：本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的单触发低能触发器电路来捕获和存储输入信号电平的技术。单触发低能触发器电路仅对时钟信号提供三个晶体管栅极负载，并且当输入信号保持不变时，内部节点都不会切换。输出信号Q在上升时钟沿使用单触发子电路设置或复位。时钟信号为低电平时，可以设置置位或复位，并在时钟的上升沿触发置位或复位。

89. 发明授权

US07920555B2 Composite trunking 有权
标题翻译：复合干线
公开(公告)号：US07920555B2
公开(公告)日：2011-04-05
申请号：US10021205
申请日：2001-12-07
申请人： Philip P. Carvey , William J. Dally , Larry R. Dennison
发明人： Philip P. Carvey , William J. Dally , Larry R. Dennison
IPC分类号： H04L12/50
CPC分类号： H04L45/04 , Y10S370/902
摘要： An Internet router treats plural output ports with a common destination as a composite port. A routing table uses the IP address to determine a composite trunk to which the packet is to be forwarded. A forwarding table identifies a route along a routing fabric within the router to a specific output port of the composite port. Output ports and fabric routes are selected to maintain order within a flow by routing the flow along a single fabric route to a single output trunk. The forwarding table may favor output ports which are nearest to a packet input port, and the forwarding table may be modified to dynamically balance load across the trunks of a composite trunk.
摘要翻译：互联网路由器将具有公共目的地的多个输出端口视为复合端口。路由表使用IP地址来确定要转发数据包的组合中继。转发表将沿着路由器内的路由结构的路由标识到复合端口的特定输出端口。选择输出端口和结构路由以通过将流沿单个结构路由路由到单个输出中继来维持流中的顺序。转发表可能有利于最接近分组输入端口的输出端口，并且可以修改转发表以动态平衡复合中继线的中继线上的负载。

90. 发明申请

US20110051794A1 Digital Transmitter 有权
公开(公告)号：US20110051794A1
公开(公告)日：2011-03-03
申请号：US12942607
申请日：2010-11-09
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L25/04
CPC分类号： H04L25/03019 , H04B1/0483 , H04B1/1081 , H04B1/16 , H04B3/04 , H04L1/0042 , H04L25/0272 , H04L25/0282 , H04L25/03025 , H04L25/03343 , H04L25/03878 , H04L25/03885 , H04L27/01
摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式