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    • 83. 发明申请
    • DATA PROCESSOR
    • 数据处理器
    • US20110107064A1
    • 2011-05-05
    • US12915158
    • 2010-10-29
    • Hiroaki NAKAYAYuki KondohMakoto Ishikawa
    • Hiroaki NAKAYAYuki KondohMakoto Ishikawa
    • G06F9/30
    • G06F9/382G06F9/30149G06F9/3017G06F9/30185G06F9/3802G06F9/3822
    • The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.
    • 本发明在包括具有前缀的指令的指令集上实现有效的超标量指令问题和低功耗。 采用指令取出单元,其判定指令码是否是前缀码,也可以是除了指令码以外的指令码,并输出确定结果和16位指令码。 与此同时,基于确定结果解码指令代码的解码器和分别解码前缀码的解码器分别设置。 此外,在固定长度指令代码(如16位修改)之前,将前缀提供给每个解码器。 与前缀码相邻的固定长度指令代码被提供给与前缀码的解码器相同的流水线的每个解码器。