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81. 发明申请

US20080087998A1 Interconnection between different circuit types 失效
标题翻译：不同电路类型之间的互连
公开(公告)号：US20080087998A1
公开(公告)日：2008-04-17
申请号：US11548994
申请日：2006-10-12
申请人： Theodore I. Kamins , Shashank Sharma
发明人： Theodore I. Kamins , Shashank Sharma
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： H01L23/49827 , H01L2224/13017 , H01L2224/1308 , H01L2924/0002 , H01L2924/00
摘要： A hybrid-scale electronic circuit, an internal electrical connection and a method of electrically interconnecting employ an interconnect having a tapered shape to electrically connect between different-scale circuits. The interconnect has a first end with an end dimension that is larger than an end dimension of an opposite, second end of the interconnect. The larger first end of the interconnect connects to an electrical contact of a micro-scale circuit and the second end of the interconnect connects to an electrical contact of a nano-scale circuit.
摘要翻译：混合比例电子电路，内部电连接和电互连的方法采用具有锥形形状的互连以在不同尺度的电路之间电连接。互连具有第一端，端部尺寸大于互连的相对的第二端的端部尺寸。互连的较大的第一端连接到微尺度电路的电接触，并且互连的第二端连接到纳米级电路的电接触。

82. 发明授权

US07190075B2 Method of forming smooth polycrystalline silicon electrodes for molecular electronic devices 失效
标题翻译：形成用于分子电子器件的光滑多晶硅电极的方法
公开(公告)号：US07190075B2
公开(公告)日：2007-03-13
申请号：US11127917
申请日：2005-05-11
申请人： Theodore I. Kamins
发明人： Theodore I. Kamins
IPC分类号： H01L23/48
CPC分类号： H01L21/02667 , B82Y10/00 , H01L21/02532 , H01L21/2022 , H01L21/76838
摘要： A method is provided for forming smooth polycrystalline silicon electrodes for molecular electronic devices. The method comprises: depositing a silicon layer in an amorphous form; forming a native oxide on a surface of the amorphous silicon layer at a temperature between room temperature to 500° C.; and converting the amorphous silicon to polycrystalline silicon by heat-treating at a temperature in a range of 600° to 800° C. for a period of time in a range of 1 minute to 24 hrs, with higher temperatures associated with shorter times, in an inert atmosphere. The method converts the amorphous form of silicon to the higher conductivity polycrystalline form, while retaining the smoothness associated with the amorphous form.
摘要翻译：提供了一种形成用于分子电子器件的平滑多晶硅电极的方法。该方法包括：沉积非晶形式的硅层; 在室温至500℃的温度下在非晶硅层的表面上形成天然氧化物; 在600〜800℃的温度范围内，在1分钟〜24小时的范围内进行热处理，将该非晶硅转化为多晶硅，在较短的时间内与较高的温度相比，在惰性气氛。该方法将无定形形式的硅转化为较高电导率的多晶形式，同时保持与无定形形式相关的平滑度。

83. 发明授权

US07087920B1 Nanowire, circuit incorporating nanowire, and methods of selecting conductance of the nanowire and configuring the circuit 失效
标题翻译：纳米线，并入纳米线的电路，以及选择纳米线的电导和配置电路的方法
公开(公告)号：US07087920B1
公开(公告)日：2006-08-08
申请号：US11038644
申请日：2005-01-21
申请人： Theodore I. Kamins
发明人： Theodore I. Kamins
IPC分类号： H01L29/02
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/02 , G11C2213/16 , G11C2213/17 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/685 , H01L29/78696 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/148 , H01L45/1616 , H01L45/165 , Y10S977/762 , Y10S977/938 , Y10S977/943
摘要： A nanowire includes a single crystalline semiconductor material having an exterior surface and an interior region and at least one dopant atom. At least a portion of the nanowire thermally switches between two conductance states; a high conductance state, where a high fraction of the dopant atoms is in the interior region, and a low conductance state, where a lower fraction of the dopant atoms is at the interior region and a higher fraction of the atoms is at the exterior surface. A method to select the conductance of the nanowire increases a temperature of the nanowire at least in a local region to a programming temperature to thermally activate diffusion of a dopant atom into a bulk region of the single crystalline semiconductor material and decreases the temperature of the nanowire at least in the local region to a second temperature to immobilize dopant atoms in the bulk region, the second temperature being below the programming temperature, wherein immobilized dopant atoms in the bulk region produce a desired high or low conductance state in the nanowire. The method can be used to initially configure and to reconfigure a circuit incorporating the nanowire.
摘要翻译：纳米线包括具有外表面和内部区域以及至少一个掺杂剂原子的单晶半导体材料。纳米线的至少一部分在两个电导状态之间热切换; 高电导状态，其中高分子量的掺杂剂原子在内部区域，并且低电导状态，其中掺杂剂原子的较低部分在内部区域，较高部分的原子位于外部表面。选择纳米线的电导的方法至少在局部区域将纳米线的温度增加到编程温度，以热激活掺杂剂原子扩散到单晶半导体材料的主体区域并降低纳米线的温度至少在局部区域到第二温度以固定化区域中的掺杂剂原子，第二温度低于编程温度，其中本体区域中固定的掺杂剂原子在纳米线中产生期望的高或低导电状态。该方法可用于初始配置和重新配置纳入纳米线的电路。

84. 发明授权

US06885031B2 Integrated circuit including single crystal semiconductor layer on non-crystalline layer 失效
标题翻译：集成电路包括非晶层上的单晶半导体层
公开(公告)号：US06885031B2
公开(公告)日：2005-04-26
申请号：US10638858
申请日：2003-08-09
申请人： Theodore I. Kamins
发明人： Theodore I. Kamins
IPC分类号： C30B1/00 , C30B7/00 , C30B13/00 , C30B25/02 , C30B25/18 , C30B29/06 , H01L21/20 , H01L21/205 , H01L31/112
CPC分类号： C30B29/06 , C30B1/00 , C30B7/00 , C30B7/005 , C30B13/00 , C30B25/18 , C30B29/54 , H01L21/02422 , H01L21/02499 , H01L21/02532 , H01L21/02609
摘要： A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.
摘要翻译：描述了在非晶体表面上形成单晶半导体膜的方法。根据该方法，在非结晶表面上沉积结合成核位点的有序阵列的模板层，并且从成核位点的有序阵列在非结晶表面上形成单晶半导体膜。还描述了通过该方法形成的一个或多个单晶半导体层的集成电路。

85. 发明授权

US06815750B1 Field effect transistor with channel extending through layers on a substrate 失效
标题翻译：场效应晶体管，其通道延伸穿过衬底上的层
公开(公告)号：US06815750B1
公开(公告)日：2004-11-09
申请号：US10155416
申请日：2002-05-22
申请人： Theodore I. Kamins
发明人： Theodore I. Kamins
IPC分类号： H01L31119
CPC分类号： H01L29/78696 , H01L29/0673 , H01L29/0676 , H01L29/66742 , H01L29/6675 , H01L29/78642
摘要： A field effect transistor (FET) has a channel formed in a pore extending up from a conductive portion of a substrate through a stack of planar layers including a first insulating layer, a gate layer, and a second insulating layer. The pore can be upright or inclined relative to the layers. A nanoparticle used for a mask of a directional etching process ultimately defines the size of the pore and therefore the channel width. The substrate or a doped region of the substrate formed immediately beneath the channel can be a source/drain of the FET with the other drain/source being a doped region adjacent the top of the channel. The gate layer can form the gate or can contact a separate gate inside the pore.
摘要翻译：场效应晶体管（FET）具有形成在从衬底的导电部分向上延伸通过包括第一绝缘层，栅极层和第二绝缘层的平面层的堆叠的孔的沟道。孔可相对于层直立或倾斜。用于定向蚀刻工艺的掩模的纳米颗粒最终限定了孔的尺寸并因此限定了通道宽度。在沟道正下方形成的衬底或衬底的掺杂区域可以是FET的源极/漏极，而另一个漏极/源极是与沟道顶部相邻的掺杂区域。栅极层可以形成栅极或者可以接触孔内的单独栅极。

86. 发明授权

US06315384B1 Thermal inkjet printhead and high-efficiency polycrystalline silicon resistor system for use therein 失效
标题翻译：热喷墨打印头和高效多晶硅电阻系统
公开(公告)号：US06315384B1
公开(公告)日：2001-11-13
申请号：US09604306
申请日：2000-06-26
申请人： Ravi Ramaswami , Victor Joseph , Min Cao , Theodore I. Kamins , John P. Whitlock , Anil Prem
发明人： Ravi Ramaswami , Victor Joseph , Min Cao , Theodore I. Kamins , John P. Whitlock , Anil Prem
IPC分类号： B41J205
CPC分类号： C07C323/12 , B41J2/14129 , C07C323/62 , C07D277/34 , C07D417/12
摘要： A highly-efficient thermal inkjet printhead. The printhead includes a primary layer of polycrystalline silicon (preferably doped) having at least one portion thereof which functions as an ink expulsion resistor. Positioned over and above the primary layer is a secondary layer of material having at least one section produced from a selected metal silicide compound and at least another section fabricated from undoped polycrystalline silicon. The metal silicide-containing section functions as an interconnect structure and is operatively connected to the resistor in the primary layer (which is positioned beneath the secondary layer). The undoped polycrystalline silicon section is at least partially aligned over and above the resistor. As a result, the resistor is “buried” beneath the secondary layer and the various portions thereof. This system provides improved reliability, greater dimensional simplicity, optimized electrical/thermal properties, and superior versatility.
摘要翻译：高效热敏打印头。打印头包括具有至少一部分作为墨水排出电阻器的多晶硅（优选掺杂）的主层。位于主层之上和之上的是具有由所选择的金属硅化物化合物和至少另一部分由未掺杂的多晶硅制成的至少一个部分的第二层材料。含金属硅化物的部分用作互连结构，并且可操作地连接到初级层（位于次级层下面）的电阻器。未掺杂的多晶硅部分至少部分地对准电阻器上方和上方。结果，电阻器被“掩埋”在次级层及其各个部分之下。该系统提供更高的可靠性，更大的尺寸简单性，优化的电/热性能，以及出色的通用性。

87. 发明授权

US5557596A Ultra-high density storage device 失效
标题翻译：超高密度存储设备
公开(公告)号：US5557596A
公开(公告)日：1996-09-17
申请号：US501432
申请日：1995-07-12
申请人： Gary Gibson , Theodore I. Kamins , Marvin S. Keshner , Steven L. Neberhuis , Craig M. Perlov , Chung C. Yang
发明人： Gary Gibson , Theodore I. Kamins , Marvin S. Keshner , Steven L. Neberhuis , Craig M. Perlov , Chung C. Yang
IPC分类号： G11B9/10 , G11B9/14 , H01J19/32 , H01J21/10 , H01L27/10 , G11B7/00 , G11C11/42
CPC分类号： G11B9/10 , Y10S977/849 , Y10S977/861 , Y10S977/863 , Y10S977/869 , Y10S977/881 , Y10S977/943
摘要： A storage device including many field emitters in close proximity to a storage medium, and a micromover, all in a partial vacuum. Each field emitter can generate an electron beam current. The storage medium has many storage areas on it, with each field emitter responsible for a number of storage areas. Also, each storage area can be in a number of different states to represent the information stored in that area. In storing information to the storage device, the power density of an electron beam current is increased to change the state of the storage area bombarded by the electron beam current. In reading information from the device, the power density of the electron beam current is reduced to generate a signal current from the storage area bombarded by the electron beam current. During reading, the power density is selected to be low enough so that no writing occurs. The magnitude of the signal current depends on the states of the storage area. The information stored in the storage area is read by measuring the magnitudes of the signal current. Finally, the micromover can scan the storage medium with respect to the field emitters so that each field emitter can access many storage areas.
摘要翻译：一种存储装置，包括紧邻存储介质的许多场发射器和全部处于部分真空中的微型扫描器。每个场发射器可以产生电子束电流。存储介质上有许多存储区域，每个场发射器负责多个存储区域。此外，每个存储区域可以是多个不同的状态，以表示存储在该区域中的信息。在将信息存储到存储装置中时，电子束电流的功率密度增加以改变由电子束电流轰击的存储区域的状态。在从器件读取信息时，电子束电流的功率密度降低，以产生由电子束电流轰击的存储区域的信号电流。在读取期间，功率密度被选择为足够低，使得不会发生写入。信号电流的大小取决于存储区域的状态。通过测量信号电流的大小来读取存储在存储区域中的信息。最后，微型扫描器可以相对于场发射器扫描存储介质，使得每个场发射器可以访问许多存储区域。

88. 发明授权

US5084411A Semiconductor processing with silicon cap over Si.sub.1-x Ge.sub.x Film 失效
标题翻译：半导体处理与Si1-xGex薄膜上的硅帽
公开(公告)号：US5084411A
公开(公告)日：1992-01-28
申请号：US277593
申请日：1988-11-29
申请人： Stephen Laderman , Martin Scott , Theodore I. Kamins , Judy L. Hoyt , Clifford A. King , James F. Gibbons , David B. Noble
发明人： Stephen Laderman , Martin Scott , Theodore I. Kamins , Judy L. Hoyt , Clifford A. King , James F. Gibbons , David B. Noble
IPC分类号： H01L21/20 , H01L21/205
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0245 , H01L21/0262 , Y10S148/015 , Y10S438/902
摘要： Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si.sub.1-x Ge.sub.x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625.degree. to 1000.degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap. Some differences in the number of misfit dislocations generated in CVD and MBE films were observed after annealing uncapped layers at temperatures between 625.degree. and 825.degree. C.
摘要翻译：根据以下发现提供了具有硅到SiGe合金异质结的改进的器件。使用X射线形貌和透射电子显微镜来定量由作为化学气相沉积技术的限制反应处理（LRP）形成的生长的Si1-xGex膜中的失配位错间隔。这些分析技术也用于研究在通过LRP和分子束外延（MBE）生长的材料退火期间的位错形成。失配位错首先出现在生长材料中的厚度对于两种生长技术是相似的。在625℃至1000℃的范围内快速热退火后，还研究了封盖和未封装的膜的热稳定性。在含有外延硅帽的样品中观察到不合适的位错显着更少。在625°和825℃之间的温度下退火未封层后，观察到在CVD和MBE膜中产生的失配位错数量的一些差异。

89. 发明授权

US4087571A Controlled temperature polycrystalline silicon nucleation 失效
标题翻译：控制温度多晶硅成核
公开(公告)号：US4087571A
公开(公告)日：1978-05-02
申请号：US589821
申请日：1975-06-24
申请人： Theodore I. Kamins , Juliana Manoliu
发明人： Theodore I. Kamins , Juliana Manoliu
IPC分类号： H01L21/225 , H01L21/3205 , H01L21/3215 , H01L21/205
CPC分类号： H01L21/32055 , H01L21/2257 , H01L21/32155 , Y10S148/053 , Y10S148/115 , Y10S148/122 , Y10S148/153
摘要： The diffusivity of an impurity in a layer of polycrystalline silicon is controlled by forming the polycrystalline silicon on a thin nucleating layer of polycrystalline silicon possessing a maximum {110} texture.
摘要翻译：通过在具有最大{110}纹理的多晶硅的薄成核层上形成多晶硅来控制多晶硅层中杂质的扩散性。

90. 发明申请

US20140017558A1 Diatomaceous Ionic Gel Separation Layer for Energy Storage Devices and Printable Composition Therefor 审中-公开
标题翻译：用于储能装置的硅藻土离子凝胶分离层及其可印刷组合物
公开(公告)号：US20140017558A1
公开(公告)日：2014-01-16
申请号：US13571308
申请日：2012-08-09
申请人： Vera Nicholaevna Lockett , Mark David Lowenthal , Neil O. Shotton , William Johnstone Ray , Theodore I. Kamins
发明人： Vera Nicholaevna Lockett , Mark David Lowenthal , Neil O. Shotton , William Johnstone Ray , Theodore I. Kamins
IPC分类号： H01M10/0565 , H01M10/056 , H01M2/16
CPC分类号： H01G11/52 , H01G11/60 , H01G11/62 , H01G11/84 , H01M2/145 , H01M2/16 , H01M2/164 , H01M2/1646 , H01M2/1653 , H01M2/166 , H01M2/1686 , H01M10/0525 , H01M10/056 , H01M10/0565 , H01M10/0568 , H01M10/0569 , H01M2300/0025 , H01M2300/0028 , H01M2300/0085 , Y02E60/13
摘要： Representative embodiments provide a liquid or gel separator utilized to separate and space apart first and second conductors or electrodes of an energy storage device, such as a battery or a capacitor. A representative liquid or gel separator comprises a plurality of particles selected from the group consisting of: diatoms, diatomaceous frustules, diatomaceous fragments, diatomaceous remains, and mixtures thereof; a first, ionic liquid electrolyte; and a polymer or, in the printable composition, a polymer or a polymeric precursor. Another representative embodiment further comprises a second electrolyte different from the first electrolyte; the first and second electrolytes comprise zinc tetrafluoroborate salt in 1-ethyl-3-methylimidalzolium tetrafluoroborate ionic liquid; and the polymer comprises polyvinyl alcohol (“PVA”) or polyvinylidene fluoride (“PVFD”). Additional components, such as additional electrolytes and solvents, may also be included.
摘要翻译：代表性的实施例提供了用于分离和分开能量存储装置（例如电池或电容器）的第一和第二导体或电极的液体或凝胶分离器。代表性的液体或凝胶分离器包括多个选自以下的颗粒：硅藻，硅藻土，硅藻土碎片，硅藻土及其混合物; 第一种离子液体电解质; 和聚合物或在可印刷组合物中的聚合物或聚合物前体。另一个代表性实施例还包括不同于第一电解质的第二电解质; 第一和第二电解质包括在1-乙基-3-甲基咪唑鎓四氟硼酸盐离子液体中的四氟硼酸锌盐; 聚合物包括聚乙烯醇（“PVA”）或聚偏二氟乙烯（“PVFD”）。还可以包括另外的组分，例如附加的电解质和溶剂。

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