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81. 发明申请

US20070053141A1 Electric double layer capacitor 失效
标题翻译：双电层电容器
公开(公告)号：US20070053141A1
公开(公告)日：2007-03-08
申请号：US11517352
申请日：2006-09-08
申请人： Takeshi Fujino
发明人： Takeshi Fujino
IPC分类号： H01G9/00
CPC分类号： H01G9/058 , H01G9/038 , H01G9/155 , H01G11/62 , Y02E60/13
摘要： An electric double layer capacitor suppresses gas generation by decomposition of the electrolyte solution in the capacitor and has a superior performance maintaining ratio. In the electric double layer capacitor including activated carbon polarized electrodes and nonaqueous electrolyte solution, an antacid agent consisting of alkali metal salt of an organic acid is contained in the capacitor.
摘要翻译：电双层电容器通过电容器中的电解质溶液的分解来抑制气体产生，并且具有优异的性能保持率。在包括活性炭极化电极和非水电解质溶液的双电层电容器中，电容器中含有由有机酸的碱金属盐构成的抗酸剂。

82. 发明授权

US07067051B2 Process for producing carbonized product used for producing activated carbon for electrode of electric double-layer capacitor, and organic material for carbonized product 失效
标题翻译：用于生产用于双电层电容器电极活性炭的碳化产品的生产方法和用于碳化产品的有机材料
公开(公告)号：US07067051B2
公开(公告)日：2006-06-27
申请号：US10687740
申请日：2003-10-20
申请人： Takeshi Fujino
发明人： Takeshi Fujino
IPC分类号： C10C1/00
CPC分类号： C01B32/342
摘要： To produce a carbonized product used for producing activated carbon for en electrode of an electric double-layer capacitor, a condensed polycyclic aromatic pitch having an optical anisotropic rate Oa in a range of 1%≦Oa≦90% and a softening point Ts in a range of 140° C.≦Ts≦260° C. is subjected to an oxygen crosslinking treatment at a heating temperature Th set at Th
摘要翻译：为了制造用于制造电双层电容器的电极的活性炭的碳化产物，具有1％<= Oa <= 90％范围内的光学各向异性率Oa和软化点Ts的缩合多环芳香沥青在140℃的范围内，在设定为Th <260℃的加热温度Th下进行氧交联处理，以提供具有轻组分的碳化产物的有机材料含量L等于或高于14.5重量％，并且将有机材料以设定在Rt> = 500℃/小时的升温速率Rt和设定在一定范围内的加热温度Th进行碳化处理对于加热时间t设定为t <= 2小时，<= Th <= 1,000℃。

83. 发明申请

US20060013030A1 Refresh-free dynamic semiconductor memory device 失效
公开(公告)号：US20060013030A1
公开(公告)日：2006-01-19
申请号：US11165273
申请日：2005-06-24
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C5/06
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

84. 发明授权

US06980454B2 Low-power consumption semiconductor memory device 失效
公开(公告)号：US06980454B2
公开(公告)日：2005-12-27
申请号：US10949365
申请日：2004-09-27
申请人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
发明人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/405 , G11C7/12 , G11C11/409 , G11C11/4094 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4094 , G11C7/12
摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

85. 发明申请

US20050276624A1 Image heating apparatus and fixing apparatus 有权
标题翻译：图像加热装置和定影装置
公开(公告)号：US20050276624A1
公开(公告)日：2005-12-15
申请号：US11142394
申请日：2005-06-02
申请人： Takeshi Fujino
发明人： Takeshi Fujino
IPC分类号： G03G15/20
CPC分类号： G03G15/2021 , G03G15/2039
摘要： An image heating apparatus including: a first image heating unit for heating a toner image on a recording material; a second image heating unit for heating the toner image on the recording material heated by the first image heating unit; and a detecting unit for detecting a temperature of the first image heating unit, wherein the image heating apparatus is operable to a correcting mode in which a temperature of the second image heating unit is corrected in accordance with the detected temperature of the first image heating unit.
摘要翻译：一种图像加热装置，包括：第一图像加热单元，用于加热记录材料上的调色剂图像; 第二图像加热单元，用于加热由第一图像加热单元加热的记录材料上的调色剂图像; 以及检测单元，用于检测第一图像加热单元的温度，其中图像加热装置可操作到根据第一图像加热单元的检测温度校正第二图像加热单元的温度的校正模式。

86. 发明申请

US20050117275A1 Process for production of activated carbon for electrode for electric double layer capacitor and carbon material thereof 审中-公开
标题翻译：双电层电容器及其碳材料用电极活性炭的制造方法
公开(公告)号：US20050117275A1
公开(公告)日：2005-06-02
申请号：US10982755
申请日：2004-11-05
申请人： Takeshi Fujino , Ryusuke Shigematsu , Koichi Kanno
发明人： Takeshi Fujino , Ryusuke Shigematsu , Koichi Kanno
IPC分类号： C01B31/02 , C01B31/08 , C01B31/12 , H01G11/22 , H01G11/24 , H01G11/34 , H01G11/38 , H01G11/42 , H01G11/44 , H01G11/86 , H01G9/00
CPC分类号： H01G9/058 , C01B32/30 , C01B32/33 , C01B32/342 , H01G11/34 , Y02E60/13
摘要： A carbon material for an electric double layer capacitor in which a ratio of hydrogen atoms to carbon atoms, H/C, is not less than 0.2 and a true specific gravity is not less than 1.50 g/ml, is provided. Furthermore, a process for production of an activated carbon for an electric double layer capacitor in which a carbon material having a ratio of hydrogen atoms to carbon atoms, H/C, not less than 0.2, and a true specific gravity not less than 1.5 g/ml is activated, is provided.
摘要翻译：提供了其中氢原子与碳原子的比例H / C不小于0.2且真实比重不低于1.50g / ml的双电层电容器用碳材料。此外，制造双电层电容器的活性炭的方法，其中具有氢原子与碳原子的比例H / C，不小于0.2的碳材料和真比重不小于1.5g / ml被激活。

87. 发明授权

US06674685B2 Semiconductor memory device having write column select gate 有权
标题翻译：具有写入列选择栅极的半导体存储器件
公开(公告)号：US06674685B2
公开(公告)日：2004-01-06
申请号：US10222840
申请日：2002-08-19
申请人： Takeshi Fujino
发明人： Takeshi Fujino
IPC分类号： G11C800
CPC分类号： G11C11/4076 , G11C7/12 , G11C7/22 , G11C11/4097 , G11C2207/002 , G11C2207/229
摘要： A DRAM includes a sense amplifier which is activated when first and second nodes are set respectively to L and H levels to amplify a potential difference between paired bit lines. The DRAM further includes a write column select gate which is activated when the first node is set to L level to write a data signal on a pair of write data lines into a corresponding sense amplifier when a corresponding write column select line is set to H level. In this way, the data signal can be written into the sense amplifier simultaneously with sensing and amplification of memory cell data, which can enhance the random access rate.
摘要翻译： DRAM包括读取放大器，当第一和第二节点分别被设置为L和H电平时，该放大器被激活，以放大成对位线之间的电位差。 DRAM还包括写入列选择栅极，当第一个节点被设置为L电平时，当对应的写入列选择线被设置为H电平时，将写入数据线上的数据信号写入相应的读取放大器。以这种方式，数据信号可以与存储单元数据的感测和放大同时写入读出放大器，这可以增强随机存取速率。

88. 发明授权

US06649984B1 Logic-merged memory 有权
标题翻译：逻辑合并记忆
公开(公告)号：US06649984B1
公开(公告)日：2003-11-18
申请号：US09632333
申请日：2000-08-03
申请人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
发明人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
IPC分类号： H01L29792
CPC分类号： H01L27/10897 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C29/12
摘要： In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.
摘要翻译：在存储器电路中，以与逻辑晶体管相同的工艺形成的晶体管用于外围电路，除了要被提供高电压的区域之外。因此，可以简化制造过程，并且提供以高速运行的逻辑合并存储器。

89. 发明授权

US06643214B2 Semiconductor memory device having write column select gate 失效
公开(公告)号：US06643214B2
公开(公告)日：2003-11-04
申请号：US10166122
申请日：2002-06-11
申请人： Yasuhiko Taito , Takeshi Fujino , Masaru Haraguchi
发明人： Yasuhiko Taito , Takeshi Fujino , Masaru Haraguchi
IPC分类号： G11C800
CPC分类号： G11C7/1096 , G11C7/1048 , G11C7/1078 , G11C11/4096 , G11C2207/002 , G11C2207/229
摘要： This DRAM includes a driver circuit which is provided to be common to a plurality of columns and which lowers level of one of selected first and second bit lines to “L” level in accordance with potentials of first and second write data lines. Therefore, as compared with a conventional DRAM in which a driver circuit is provided for each column, the number of transistors is decreased and a layout area is reduced.

90. 发明授权

US06404695B1 Semiconductor memory device including a plurality of memory blocks arranged in rows and columns 失效
标题翻译：半导体存储器件包括以行和列排列的多个存储块
公开(公告)号：US06404695B1
公开(公告)日：2002-06-11
申请号：US09877026
申请日：2001-06-11
申请人： Takeshi Fujino , Akira Yamazaki
发明人： Takeshi Fujino , Akira Yamazaki
IPC分类号： G11C800
CPC分类号： G11C11/4087
摘要： A DRAM includes two main column selecting lines provided at each sense amplifier zone, eight sub column selecting lines provided at each sense amplifier zone to correspond to each memory block, two sub decoder column selecting lines provided at each sub decoder zone, a sub column decoder provided at each crossing portion of the sense amplifier zone and the sub decoder zone to select one sub column selecting line from corresponding eight sub column selecting lines in accordance with a signal from the two main column selecting lines and the two sub decoder column selecting lines. The area of the sense amplifier zone can be reduced compared to that of a conventional DRAM in which all signal lines for column selection were provided at a sense amplifier zone.
摘要翻译： DRAM包括在每个读出放大器区域提供的两个主列选择线，在每个读出放大器区域处提供的八个子列选择线，以对应于每个存储块，在每个子解码器区提供的两个子解码器列选择线，子列解码器设置在感测放大器区域和子解码器区域的每个交叉部分处，以根据来自两个主列选择线和两个子解码器列选择线的信号从相应的八个子列选择线中选择一个子列选择线。与传统DRAM相比，读出放大器区域的面积可以减少，其中用于列选择的所有信号线都设置在读出放大器区域。

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