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81. 发明授权

US5254880A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5254880A
公开(公告)日：1993-10-19
申请号：US863705
申请日：1992-04-03
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02 , H03K3/01 , H03K5/01
CPC分类号： G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , G11C5/147 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

82. 发明授权

US4958325A Low noise semiconductor memory 失效
标题翻译：低噪声半导体存储器
公开(公告)号：US4958325A
公开(公告)日：1990-09-18
申请号：US238375
申请日：1988-08-31
申请人： Yoshinobu Nakagome , Kiyoo Itoh , Masakazu Aoki , Shin'ichi Ikenaga , Masashi Horiguchi , Hitoshi Tanaka
发明人： Yoshinobu Nakagome , Kiyoo Itoh , Masakazu Aoki , Shin'ichi Ikenaga , Masashi Horiguchi , Hitoshi Tanaka
IPC分类号： G11C7/18 , G11C11/4097
CPC分类号： G11C7/18 , G11C11/4097
摘要： A highly integrated semiconductor memory, particularly, a low noise dynamic memory. As the density of integration of the dynamic memory increases, the distance between data lines decreases and a new type of noise, which has hitherto been thought little of, displays itself. To cope with this problem in the semiconductor memory comprising a plurality of pairs of data lines arranged in substantially parallel relationship with each other, respective pairs having substantially the same electric characteristics, connection means provided in association with the respective data line pairs, a plurality of word lines laid to extend perpendicularly to the data line pairs, at least one memory cell connected to at least one of intersections of the word lines with data lines of the pairs, and a plurality of sense amplifier means respectively connected to the data line pairs to differentially detect signal voltages appearing on each data line pair, the plural data line pairs have an alternate arrangement of a pair of data lines transposed at an even number of places and a pair of data lines transposed at an odd number of places, and the sense amplifier means is operative to change voltage on one of the data lines of a pair to a high-level voltage and voltage on the other of the data lines of the pair of a low-level voltage.
摘要翻译：高度集成的半导体存储器，特别是低噪声动态存储器。随着动态存储器的集成密度增加，数据线之间的距离减小，而迄今为止被认为很少的新型噪声显示出来。为了在包括彼此基本上平行关系的多对数据线的半导体存储器中应对这个问题，具有基本上相同电特性的各对具有与各个数据线对相关联地设置的连接装置，与数据线对垂直延伸的字线，至少一个存储单元连接到字线与该对的数据线的交点中的至少一个，以及分别连接到数据线对的多个读出放大器装置差分检测每个数据线对上出现的信号电压，多个数据线对具有在偶数个位置处置换的一对数据线和在奇数个位置处置换的一对数据线的交替排列，并且感测放大器装置可操作以将一对数据线之一上的电压改变为ot上的高电平电压和电压她的数据线是一对低电平的电压。

83. 发明授权

US4965769A Semiconductor memory capable of high-speed data erasing 失效
标题翻译：具有高速数据擦除功能的半导体存储器
公开(公告)号：US4965769A
公开(公告)日：1990-10-23
申请号：US278025
申请日：1988-11-30
申请人： Jun Etoh , Kiyoo Itoh , Masakazu Aoki , Ryoichi Hori
发明人： Jun Etoh , Kiyoo Itoh , Masakazu Aoki , Ryoichi Hori
IPC分类号： G11C11/401 , G11C7/20 , G11C8/12 , G11C11/404 , G11C11/4072 , G11C11/408 , H01L27/10
CPC分类号： G11C7/20 , G11C11/4072 , G11C11/4087 , G11C8/12
摘要： A semiconductor memory having a plurality of word lines, and a plurality of data lines arranged to intersect the word lines. Memory cells are arranged at nodes of the word lines and the data lines. Each of the memory cells has a field effect transistor and a capacitor. A word line multiple selection circuit is provided for selecting a plurality of the word lines. The multiple selection circuit simultaneously accesses all of the memory cells by selecting all the word lines of a memory array when a semiconductor memory is in a clear mode. In the clear mode a detector selects data lines of the memory array. A plate voltage control circuit controls a voltage at one plate of each of the capacitors in the memory cells. The plate control circuit changes a voltage at the plate to a preselected clear mode voltage when a semiconductor memory is in a clear mode. It is a feature of the invention that preselected data is written in the memory cells by data communication through the data lines during the clear mode. The preselected data includes at least one "1" data of the preselected data written in the memory cells. Subsequently to end the clear mode operation, the plate voltage control circuit changes the plate voltage for normal operations.
摘要翻译：一种具有多个字线的半导体存储器和与该字线相交的多条数据线。存储单元被布置在字线和数据线的节点处。每个存储单元都具有场效应晶体管和电容器。提供用于选择多个字线的字线多重选择电路。当半导体存储器处于清除模式时，多选择电路通过选择存储器阵列的所有字线来同时访问所有存储单元。在清除模式下，检测器选择存储器阵列的数据线。板电压控制电路控制存储单元中的每个电容器的一个板上的电压。当半导体存储器处于清除模式时，板控制电路将板处的电压改变为预选的清除模式电压。本发明的特征在于，在清除模式期间，通过数据线进行数据通信，将预选数据写入存储单元。预选数据包括写入存储单元的预选数据的至少一个“1”数据。随后结束清除模式操作，板电压控制电路改变正常操作的板电压。

84. 发明授权

US07388400B2 Semiconductor integrated circuits with power reduction mechanism 失效
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US07388400B2
公开(公告)日：2008-06-17
申请号：US11768981
申请日：2007-06-27
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit block includes a first MOS transistor in which a leakage current flows even under a condition that a gate voltage is equal to a source voltage. Each of the first switching elements controls the leakage current flowing through a corresponding first MOS transistor of each circuit block. Also, while one of the first switching elements is controlled to reduce the leakage current flowing through the circuit block relating to one of the first switching elements, another one of the first switching elements is controlled to allow current to flow through the circuit block relating to another one of the first switching elements. In addition, current which is allowed to flow by the another one of the first switching elements is sufficient to permit the circuit block relating to another one of the first switching elements to logically operate.
摘要翻译：具有绝对值的工作电压的半导体集成电路为2.5V以下，包括由第一和第二电力线提供工作电压的电路块和每个电路块的第一开关元件。每个电路块包括即使在栅极电压等于源极电压的条件下漏电流也流过的第一MOS晶体管。每个第一开关元件控制流过每个电路块的对应的第一MOS晶体管的漏电流。此外，虽然控制第一开关元件中的一个以减少流过与第一开关元件之一相关的电路块的漏电流，但是第一开关元件中的另一个被控制以允许电流流过与另一个是第一个开关元件。此外，允许通过另一个第一开关元件流动的电流足以允许与另一个第一开关元件相关的电路块逻辑操作。

85. 发明授权

US07215136B2 Semiconductor integrated circuits with power reduction mechanism 有权
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US07215136B2
公开(公告)日：2007-05-08
申请号：US11356100
申请日：2006-02-17
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K17/16
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.
摘要翻译：半导体集成电路芯片的功耗在2.5V或更低的工作电压下工作时，功耗降低。开关元件设置在芯片内的每个电路块中。开关元件的常数被设定为使得其断开状态下的每个开关元件中的漏电流小于相应电路块内的MOS晶体管的亚阈值电流。有源电流被提供给有源电路块，而非有效电路块的开关元件被关断。因此，非有源电路块的耗散电流被限制为相应的开关元件的漏电流值。因此，非有源电路块的耗散电流的总和小于有源电路块中的有功电流。结果，即使在活动状态下，半导体集成电路芯片的功率消耗也可以减小。

86. 发明申请

US20050094473A1 Semiconductor integrated circuits with power reduction mechanism 失效
公开(公告)号：US20050094473A1
公开(公告)日：2005-05-05
申请号：US11004823
申请日：2004-12-07
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： G11C5/14 , G11C7/06 , G11C8/08 , G11C8/12 , H03K19/00 , H03K19/003 , G11C5/00
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

87. 发明授权

US06268741B1 Semiconductor integrated circuits with power reduction mechanism 有权
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US06268741B1
公开(公告)日：2001-07-31
申请号：US09573609
申请日：2000-05-19
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K19003
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks. Since the dissipation currents of the non-active circuit blocks can be reduced while the active current is caused to flow in the active circuit blocks, the power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.
摘要翻译：本发明是为了在半导体集成电路芯片在2.5V或更低的工作电压下工作时降低功耗。为了实现该目的，在半导体集成电路芯片内的每个电路块中提供开关元件。开关元件的常数被设定为使得每个电路块的开关元件的截止状态下的漏电流小于相应电路块内的MOS晶体管的亚阈值电流。有源电流被提供给有源电路块，而非有效电路块的开关元件被关断。因此，非有源电路块的耗散电流被限制为相应的开关元件的泄漏电流值。结果，使非有源电路块的耗散电流的总和小于有源电路块中的有功电流。由于当有源电流在有源电路块中流动时，可以减小非有效电路块的耗散电流，所以即使在活动状态下也能够降低半导体集成电路芯片的功耗。

88. 发明授权

US08106678B2 Semiconductor integrated circuits with power reduction mechanism 失效
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US08106678B2
公开(公告)日：2012-01-31
申请号：US12645784
申请日：2009-12-23
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.
摘要翻译：包括第一和第二电力线的半导体器件，以及耦合在电力线之间的第一和第二电路块。第一开关元件插入在第一电路块和至少一个电源线之间，并且第二开关元件插入在第二电路块和至少一个电源线之间。第一开关元件被导通以允许第一电路块通过第一和第二电力线接收电力电压，而第二开关元件变得不导通，以防止第二电路块通过第一和第二电力接收电力电压使得流过第二电路的漏电流被抑制。

89. 发明授权

US6154062A Semiconductor integrated circuits with power reduction mechanism 有权
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US6154062A
公开(公告)日：2000-11-28
申请号：US141563
申请日：1998-08-28
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： G11C5/14 , G11C7/06 , G11C8/08 , G11C8/12 , H03K19/00 , H03K19/003 , H03K19/096 , H03K19/0948
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks. Since the dissipation currents of the non-active circuit blocks can be reduced while the active current is caused to flow in the active circuit blocks, the power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.
摘要翻译：本发明是为了在半导体集成电路芯片在2.5V或更低的工作电压下工作时降低功耗。为了实现该目的，在半导体集成电路芯片内的每个电路块中提供开关元件。开关元件的常数被设定为使得每个电路块的开关元件的截止状态下的漏电流小于相应电路块内的MOS晶体管的亚阈值电流。有源电流被提供给有源电路块，而非有效电路块的开关元件被关断。因此，非有源电路块的耗散电流被限制为相应的开关元件的泄漏电流值。结果，使非有源电路块的耗散电流的总和小于有源电路块中的有功电流。由于当有源电流在有源电路块中流动时，可以减小非有效电路块的耗散电流，所以即使在活动状态下也能够降低半导体集成电路芯片的功耗。

90. 发明授权

US5825198A Semiconductor integrated circuits with power reduction mechanism 失效
公开(公告)号：US5825198A
公开(公告)日：1998-10-20
申请号：US797051
申请日：1997-02-10
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： G11C5/14 , G11C7/06 , G11C8/08 , G11C8/12 , H03K19/00 , H03K19/003 , H03K19/017
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks. Since the dissipation currents of the non-active circuit blocks can be reduced while the active current is caused to flow in the active circuit blocks, the power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

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