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    • 83. 发明授权
    • Power semiconductor device
    • 功率半导体器件
    • US08030706B2
    • 2011-10-04
    • US12540192
    • 2009-08-12
    • Miho WatanabeMasaru IzumisawaYasuto SumiHiroshi OhtaWataru SekineWataru SaitoSyotaro OnoNana Hatano
    • Miho WatanabeMasaru IzumisawaYasuto SumiHiroshi OhtaWataru SekineWataru SaitoSyotaro OnoNana Hatano
    • H01L29/66
    • H01L29/7811H01L29/0634H01L29/1095H01L29/7802
    • A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.
    • 根据本发明实施例的半导体器件包括器件部分和端子部分。 该器件包括第一半导体层,以及形成在第一半导体层上的第二和第三半导体层,并且沿着与第一半导体层的表面平行的方向交替布置,其中器件部分设置有第一区域和第二半导体层 区域,其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个,并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N(= NA-NB) 从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值&Dgr; NC1,其是器件部分的第一区域中的差值&Dgr; N,差值&Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2,作为终端部分中的差值Dgr; N的差值&Dgr; NT满足关系 的&Dgr; NC1>&Dgr; NT>&Dgr; NC2。
    • 84. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    • 半导体器件及其制造方法
    • US20110227154A1
    • 2011-09-22
    • US13052032
    • 2011-03-18
    • Syotaro ONOWataru SaitoMunehisa YabuzakiShunji TaniuchiMiho Watanabe
    • Syotaro ONOWataru SaitoMunehisa YabuzakiShunji TaniuchiMiho Watanabe
    • H01L29/78H01L21/336
    • H01L29/7802H01L29/0634H01L29/0878H01L29/1095H01L29/66712
    • A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; a first buried layer of the first conductivity type selectively formed in the second semiconductor layer and having a first peak impurity concentration at a first depth; a second buried layer of a second conductivity type selectively formed in the second semiconductor layer and having a second peak impurity concentration at a second depth; a base layer of the second conductivity type selectively formed in the second semiconductor layer and overlapping with an upper portion of the second buried layer; a source layer of the first conductivity type selectively formed in the base layer; and a gate electrode formed on the base layer and on the second semiconductor layer above the first buried layer with a gate insulating film being interposed therebetween.
    • 一种半导体器件,包括:第一导电类型的第一半导体层; 形成在第一半导体层上的第一导电类型的第二半导体层; 第一导电类型的第一掩埋层选择性地形成在第二半导体层中,并且在第一深度处具有第一峰值杂质浓度; 第二导电类型的第二掩埋层选择性地形成在第二半导体层中,并且在第二深度具有第二峰值杂质浓度; 第二导电类型的基极层选择性地形成在第二半导体层中并与第二掩埋层的上部重叠; 选择性地形成在所述基底层中的所述第一导电类型的源极层; 以及形成在所述第一掩埋层上的所述基极层和所述第二半导体层上的栅电极,其间插入有栅极绝缘膜。
    • 85. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20110215418A1
    • 2011-09-08
    • US13029925
    • 2011-02-17
    • Wataru SAITOSyotaro OnoMunehisa YabuzakiShunji TaniuchiMiho Watanabe
    • Wataru SAITOSyotaro OnoMunehisa YabuzakiShunji TaniuchiMiho Watanabe
    • H01L27/07H01L29/72
    • H01L27/07H01L29/72
    • According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region. A distance between the embedded semiconductor region and the second major surface along a direction from the second major surface toward the first major surface becomes longer toward outside from the device region.
    • 根据一个实施例,半导体器件包括第一导电类型的第一半导体区域,第一导电类型的第二半导体区域,第一主电极,第二导电类型的第三半导体区域,第二主电极和 多个第二导电类型的嵌入式半导体区域。 第二半导体区域形成在第一半导体区域的第一主表面上。 第一主电极形成在与第一半导体区域的第一主表面相对的正面上。 第三半导体区域形成在第二半导体区域的与第一半导体区域相对的一侧的第二主表面上。 第二主电极形成为结合到第三半导体区域。 嵌入式半导体区域设置在终端区域中。 沿着从第二主表面朝向第一主表面的方向在嵌入式半导体区域和第二主表面之间的距离从器件区域向外部变长。