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81. 发明公开

US20230255032A1 MEMORY DEVICES 审中-公开
公开(公告)号：US20230255032A1
公开(公告)日：2023-08-10
申请号：US18296385
申请日：2023-04-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Meng-Han Lin , Mauricio MANFRINI , Han-Jong Chia
IPC分类号： H10B51/20 , H01L29/24 , H01L23/528 , H01L23/522 , H10B51/30
CPC分类号： H10B51/20 , H01L23/5226 , H01L23/5283 , H01L29/24 , H10B51/30
摘要： A memory device includes a multi-layer stack including a plurality of first conductive lines and a plurality of second conductive lines. The first conductive lines are stacked on one another. The second conductive lines cross over the plurality of first conductive lines, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become close to a middle portion of the multi-layer stack.

82. 发明授权

US11716857B2 Semiconductor memory device and manufacturing method thereof 有权
公开(公告)号：US11716857B2
公开(公告)日：2023-08-01
申请号：US17351121
申请日：2021-06-17
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Yu-Chien Chiu , Meng-Han Lin , Chun-Fu Cheng , Han-Jong Chia , Chung-Wei Wu , Zhiqiang Wu
IPC分类号： H10B51/20 , H01L29/06 , H10B51/10 , H10B51/30
CPC分类号： H10B51/20 , H01L29/0649 , H10B51/10 , H10B51/30
摘要： A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

83. 发明申请

US20230045420A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20230045420A1
公开(公告)日：2023-02-09
申请号：US17577410
申请日：2022-01-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Sheng-Chen Wang , Meng-Han Lin , Han-Jong Chia , Feng-Cheng Yang
IPC分类号： H01L27/11597 , H01L23/48 , H01L23/522 , H01L27/11592 , H01L27/11587
摘要： A semiconductor structure and method of forming the same are provided. The semiconductor structure includes a circuit structure, an interlayer structure and a memory structure. The circuit structure includes a substrate having semiconductor devices formed thereon; a dielectric structure disposed over the semiconductor devices; and an interconnect layer embedded in the dielectric structure and connected to the semiconductor devices. The interlayer structure is disposed over the circuit structure. The memory structure is disposed over the interlayer structure and physically separated from the circuit structure by the interlayer structure.

84. 发明授权

US11488659B2 Memory circuit and write method 有权
公开(公告)号：US11488659B2
公开(公告)日：2022-11-01
申请号：US17069312
申请日：2020-10-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shih-Lien-Linus Lu , Bo-Feng Young , Han-Jong Chia , Yu-Ming Lin , Sai-Hooi Yeong
IPC分类号： G11C11/4094 , G11C11/408 , G11C11/4099 , G11C11/4074 , G11C5/02
摘要： A memory circuit includes a memory array and a control circuit. A first column of the memory array includes a select line, first and second bit lines, a first subset of memory cells coupled to the select line and the first bit line, and a second subset of memory cells coupled to the select line and the second bit line. The control circuit is configured to simultaneously activate each of the select line and the first bit line and, during a period in which the select line and first bit line are simultaneously activated, activate a first plurality of word lines, each word line of the first plurality of word lines being coupled to a memory cell of the first subset of memory cells.

85. 发明授权

US11424268B2 Semiconductor structure and manufacturing method thereof 有权
公开(公告)号：US11424268B2
公开(公告)日：2022-08-23
申请号：US16737600
申请日：2020-01-08
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Han-Jong Chia , Yu-Ming Lin , Zhiqiang Wu , Sai-Hooi Yeong
IPC分类号： H01L27/11 , H01L27/1159 , H01L29/423 , H01L27/11507 , H01L29/66 , H01L21/28 , H01L29/78 , H01L49/02
摘要： A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate having a first surface, a plurality of ferroelectric layers stacking over the first surface, and a plurality of metal layers stacking over the first surface of the substrate, wherein each of the metal layers is on each of the ferroelectric layers. The operations of the method for manufacturing the semiconductor structure includes providing a substrate having a first surface, and forming a plurality of stack units over the first surface of the substrate The forming of each of the stack units includes the operations of forming a ferroelectric layer and forming a metal layer on the ferroelectric layer.

86. 发明申请

US20210408047A1 THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20210408047A1
公开(公告)日：2021-12-30
申请号：US17155085
申请日：2021-01-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Sheng-Chen Wang , Meng-Han Lin , Sai-Hooi Yeong , Yu-Ming Lin , Han-Jong Chia
IPC分类号： H01L27/11597 , H01L27/1159
摘要： A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.

87. 发明申请

US20210375938A1 THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20210375938A1
公开(公告)日：2021-12-02
申请号：US17159120
申请日：2021-01-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Meng-Han Lin , Chun-Fu Cheng , Feng-Cheng Yang , Sheng-Chen Wang , Yu-Chien Chiu , Han-Jong Chia
IPC分类号： H01L27/11597 , H01L27/1159 , H01L27/11582
摘要： A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars are separately located within the cell regions, and are laterally surrounded by the channel layers.

88. 发明授权

US11177267B2 Semiconductor structure and manufacturing method thereof 有权
公开(公告)号：US11177267B2
公开(公告)日：2021-11-16
申请号：US16857074
申请日：2020-04-23
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Mauricio Manfrini , Sai-Hooi Yeong , Han-Jong Chia , Chenchen Jacob Wang
IPC分类号： H01L27/11502 , G11C11/22 , H01L29/66 , H01L29/78
摘要： A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a transistor disposed within the first dielectric layer; a second dielectric layer disposed over the first dielectric layer; and a capacitor disposed within the second dielectric layer and electrically connected to the transistor, wherein the capacitor includes a first electrode, a dielectric stack disposed over the first electrode, and a second electrode disposed over the dielectric stack, the dielectric stack includes a ferroelectric layer and an electrostrictive layer. Further, a method of manufacturing a semiconductor structure includes disposing an electrostrictive material over a first electrode layer; disposing a ferroelectric material over the first electrode layer; removing a portion of the ferroelectric material to form the ferroelectric material; and removing a portion of the electrostrictive material to form the electrostrictive layer.

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