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81. 发明申请

US20130299897A1 INVERTED THIN CHANNEL MOSFET WITH SELF-ALIGNED EXPANDED SOURCE/DRAIN 有权
公开(公告)号：US20130299897A1
公开(公告)日：2013-11-14
申请号：US13468313
申请日：2012-05-10
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, JR.
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, JR.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/743 , H01L21/76898 , H01L23/485 , H01L27/12 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least with a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is thinned, and remaining portions of the bottom semiconductor layer are removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. A contact level dielectric layer is deposited on surfaces of the source and drain regions that are distal from the gate electrode, and contact vias are formed through the contact level dielectric layer.

82. 发明授权

US08536032B2 Formation of embedded stressor through ion implantation 有权
标题翻译：通过离子注入形成嵌入式应激源
公开(公告)号：US08536032B2
公开(公告)日：2013-09-17
申请号：US13155878
申请日：2011-06-08
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/265
CPC分类号： H01L29/66772 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.
摘要翻译：极薄的绝缘体上硅晶体管包括在衬底上方的掩埋氧化物层。掩埋氧化物层例如具有小于50nm的厚度。硅层在掩埋氧化物层之上。硅层上的栅极叠层包括至少形成在硅层上的栅极电介质和形成在栅极电介质上的栅极导体。栅极间隔物在硅层上具有第一部分，第二部分邻近栅极堆叠。第一升高的源极/漏极区域和第二升高的源极/漏极区域各自具有包括硅层的一部分的第一部分和与栅极间隔物相邻的第二部分。至少部分地在衬底内形成至少一个嵌入式应力器，其在硅层中形成的硅沟道区域上施加预定的应力。

83. 发明授权

US08530974B2 CMOS structure having multiple threshold voltage devices 有权
标题翻译： CMOS结构具有多个阈值电压器件
公开(公告)号：US08530974B2
公开(公告)日：2013-09-10
申请号：US13472680
申请日：2012-05-16
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/092
CPC分类号： H01L29/51 , H01L21/28176 , H01L21/823857 , H01L21/823864 , H01L29/49 , H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/7833
摘要： A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substrate. A set of vertical oxide spacers selectively formed for the first transistor device are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.
摘要翻译：具有多个阈值电压器件的互补金属氧化物半导体（CMOS）结构包括形成在半导体衬底上的第一晶体管器件和第二晶体管器件。为第一晶体管器件选择性地形成的一组垂直氧化物间隔物与第一晶体管器件的栅介质层直接接触，使得第一晶体管器件相对于第二晶体管器件具有偏移的阈值电压。

84. 发明授权

US08525292B2 SOI device with DTI and STI 有权
标题翻译：具有DTI和STI的SOI器件
公开(公告)号：US08525292B2
公开(公告)日：2013-09-03
申请号：US13088376
申请日：2011-04-17
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/00
CPC分类号： H01L21/76229 , H01L21/743 , H01L21/76232 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： An SOI structure including a semiconductor on insulator (SOI) substrate including a top silicon layer, an intermediate buried oxide (BOX) layer and a bottom substrate; at least two wells in the bottom substrate; a deep trench isolation (DTI) separating the two wells, the DTI having a top portion extending through the BOX layer and top silicon layer and a bottom portion within the bottom substrate wherein the bottom portion has a width that is larger than a width of the top portion; and at least two semiconductor devices in the silicon layer located over one of the wells, the at least two semiconductor devices being separated by a shallow trench isolation within the top silicon layer.
摘要翻译：包括绝缘体上半导体（SOI）衬底的SOI结构，包括顶部硅层，中间掩埋氧化物（BOX）层和底部衬底; 底部底物中至少有两口井; 分离两个阱的深沟槽隔离（DTI），DTI具有延伸穿过BOX层和顶部硅层的顶部和底部衬底内的底部部分，其中底部部分的宽度大于顶部以及位于所述阱之一上的所述硅层中的至少两个半导体器件，所述至少两个半导体器件由所述顶部硅层内的浅沟槽隔离隔开。

85. 发明授权

US08513765B2 Formation method and structure for a well-controlled metallic source/drain semiconductor device 有权
标题翻译：良好控制的金属源/漏极半导体器件的形成方法和结构
公开(公告)号：US08513765B2
公开(公告)日：2013-08-20
申请号：US12838844
申请日：2010-07-19
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/02
CPC分类号： H01L29/7839 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/66795
摘要： A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.
摘要翻译：用于形成半导体器件的器件和方法包括在与栅极结构相邻的沟道层上生长凸起的半导体区域。在凸起的半导体区域和栅极结构之间形成空间。在至少凸起的半导体区域上沉积金属层。凸起的半导体区域被硅化以在通道层中形成硅化物，该沟道层在对应于空间的位置处更深地延伸到沟道层中。

86. 发明授权

US08492839B2 Same-chip multicharacteristic semiconductor structures 有权
标题翻译：同芯片多特征半导体结构
公开(公告)号：US08492839B2
公开(公告)日：2013-07-23
申请号：US12861976
申请日：2010-08-24
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L27/1203
摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.
摘要翻译：在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。

87. 发明授权

US08445971B2 Field effect transistor device with raised active regions 有权
标题翻译：场效应晶体管器件具有凸起的有源区
公开(公告)号：US08445971B2
公开(公告)日：2013-05-21
申请号：US13237319
申请日：2011-09-20
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/41783 , H01L29/165 , H01L29/41775 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.
摘要翻译：一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面，第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。

88. 发明授权

US08435846B2 Semiconductor devices with raised extensions 有权
标题翻译：具有凸起延伸的半导体器件
公开(公告)号：US08435846B2
公开(公告)日：2013-05-07
申请号：US13251757
申请日：2011-10-03
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/336 , H01L21/461 , H01L29/76 , H01L29/66
CPC分类号： H01L29/4983 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7834
摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.
摘要翻译：公开了晶体管器件及其制造方法。在一种方法中，在基板上形成虚拟栅极结构。虚拟门结构的底部是底切的。此外，在基板上形成阶梯状，凸起的源极和漏极区域，以及由底切形成的至少一个底切部。去除虚拟栅极结构并在衬底上形成替换栅极。

89. 发明授权

US08394710B2 Semiconductor devices fabricated by doped material layer as dopant source 有权
标题翻译：由掺杂材料层制造的半导体器件作为掺杂剂源
公开(公告)号：US08394710B2
公开(公告)日：2013-03-12
申请号：US12819440
申请日：2010-06-21
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/2254 , H01L21/2255 , H01L21/2257 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/165 , H01L29/42392 , H01L29/66439 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/66803 , H01L29/775 , H01L29/78 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L29/78696
摘要： A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.
摘要翻译：提供一种形成半导体器件的方法，其中用于源极和漏极区的掺杂剂从掺杂的介电层引入。在一个示例中，栅极结构形成在半导体层的厚度小于10nm的SOI衬底的半导体层上。在与栅极结构相邻的半导体层的至少一部分上形成掺杂介电层。来自掺杂介电层的掺杂剂被驱动到与栅极结构相邻的半导体层的部分中。扩散到半导体中的掺杂剂提供了源极和漏极延伸区域。

90. 发明申请

US20120326230A1 SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE 审中-公开
标题翻译：绝缘子上的绝缘体与低温下形成隔离的补充金属氧化物半导体
公开(公告)号：US20120326230A1
公开(公告)日：2012-12-27
申请号：US13166714
申请日：2011-06-22
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L27/092 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions.
摘要翻译：具有隔离形成在低温下的绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）及其构造方法。一种示例性方法包括在低温下注入绝缘材料以在活性区域之间形成硅基绝缘体。

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