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    • 85. 发明申请
    • Microcomputer
    • 微电脑
    • US20050262372A1
    • 2005-11-24
    • US11085035
    • 2005-03-22
    • Hiroshi Saitoh
    • Hiroshi Saitoh
    • G06F15/78G06F1/04G06F1/14G06F1/30
    • G06F1/04
    • The present invention aims to be capable of properly measuring the cycle of an external signal even where a timer clock and a CPU clock are operated asynchronously. A timer circuit comprises a timer counter which counts a generation interval of an external signal in sync with the timer clock, a first timer register which fetches therein a counted value of the timer counter in sync with the timer clock, a second timer register which fetches therein the value of the first timer register in sync with the CPU clock, an edge detection circuit which detects a change in the level of the external signal to thereby generate an edge detection signal, and a reload control circuit which outputs a first reload control signal for reloading the count value of the timer counter into the first timer register in sync with the timer clock in accordance with the edge detection signal, and outputs a second reload control signal for reloading the value of the first timer register fetched therein by the first reload control signal into the second timer register in sync with the CPU clock, and which holds the output of the second reload control signal where the next edge detection signal is generated during the interval from after the generation of a first edge detection, the CPU reads the contents of the second timer register, and outputs the second reload control signal after the CPU has read the contents of the second timer register.
    • 本发明的目的在于能够适当地测量外部信号的周期,即使在定时器时钟和CPU时钟异步操作的情况下也是如此。 定时器电路包括定时器计数器,其与定时器时钟同步地对外部信号的产生间隔进行计数;第一定时器寄存器,其在其中取出定时器计数器的计数值与定时器时钟同步;第二定时器寄存器,其取出 其中第一定时器寄存器的值与CPU时钟同步,边缘检测电路,其检测外部信号的电平的变化从而产生边沿检测信号;以及重新加载控制电路,其输出第一重载控制信号 用于根据边缘检测信号将定时器计数器的计数值重新加载到与定时器时钟同步的第一定时器寄存器中,并且输出第二重载控制信号,用于重新加载第一定时器寄存器中通过第一重新加载获取的值 控制信号与CPU时钟同步到第二定时器寄存器中,并且其保持第二重载控制信号的输出,其中下一个边沿 在产生第一边缘检测之后的间隔期间产生检测信号,CPU读取第二定时器寄存器的内容,并且在CPU已经读取第二定时器寄存器的内容之后输出第二重新加载控制信号。
    • 88. 发明授权
    • Timer circuits for a microcomputer
    • 微计算机定时器电路
    • US06493831B1
    • 2002-12-10
    • US09414035
    • 1999-10-07
    • Hiroshi Saitoh
    • Hiroshi Saitoh
    • G06F104
    • G06F1/14
    • A select circuit selectively outputs one of a transition indication signal that is the output of an edge sense circuit of an input timer, a transition indication signal that is an output of an edge sense circuit of an output timer, and a control signal for controlling output using software. The state of activation of a switch circuit for controlling transmission of a clock signal to a counter of the output timer is then controlled by the signal selected by the select circuit.
    • 选择电路选择性地输出作为输入定时器的边沿检测电路的输出的转换指示信号,作为输出定时器的边沿检测电路的输出的转换指示信号和用于控制输出的控制信号 使用软件。 用于控制时钟信号传输到输出定时器的计数器的开关电路的激活状态然后由选择电路选择的信号控制。