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81. 发明申请

US20130111309A1 Systems and Methods for Selective Decode Algorithm Modification 有权
标题翻译：选择性解码算法修改的系统与方法
公开(公告)号：US20130111309A1
公开(公告)日：2013-05-02
申请号：US13284767
申请日：2011-10-28
申请人： Fan Zhang , Weijun Tan , Zongwang Li , Shaohua Yang
发明人： Fan Zhang , Weijun Tan , Zongwang Li , Shaohua Yang
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/1111 , G11B20/1833 , H03M13/2957 , H03M13/3715 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes a first decoder circuit and a second decoder circuit. The first decoder circuit is operable to apply a first data decode algorithm to a decoder input to yield a decoded output. The second decoder circuit is operable to apply a second data decode algorithm to a subset of the decoded output to modify at least one element of the decoded output to yield a modified decoded output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括组合数据解码器电路的数据处理系统。组合数据解码器电路包括第一解码器电路和第二解码器电路。第一解码器电路可操作以将第一数据解码算法应用于解码器输入以产生解码输出。第二解码器电路可操作以将第二数据解码算法应用于解码输出的子集，以修改解码输出的至少一个元素以产生经修改的解码输出。

82. 发明申请

US20120089888A1 Systems and Methods for Multi-Level Quasi-Cyclic Low Density Parity Check Codes 有权
标题翻译：多级准循环低密度奇偶校验码系统与方法
公开(公告)号：US20120089888A1
公开(公告)日：2012-04-12
申请号：US13316858
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
发明人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/036 , H03M13/1142 , H03M13/116
摘要： Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains.
摘要翻译：本发明的各种实施例提供了用于生成代码格式的系统和方法。所讨论的一种方法包括：本发明的各种实施例提供了用于生成代码格式的方法。这样的方法包括：接收具有陷阱集的低权重码字的指示; 选择基本矩阵的初始值; 通过初始值测试修改后的低权重码字以确定低权重码字的更新权重; 并通过初始值测试修改后的低权重码字，以确定捕获集是否保留。

83. 发明申请

US20110029837A1 Systems and Methods for Phase Dependent Data Detection in Iterative Decoding 有权
标题翻译：迭代解码中相关数据检测的系统和方法
公开(公告)号：US20110029837A1
公开(公告)日：2011-02-03
申请号：US12512235
申请日：2009-07-30
申请人： Shaohua Yang , Zongwang Li , Weijun Tan , Kelly Fitzpatrick
发明人： Shaohua Yang , Zongwang Li , Weijun Tan , Kelly Fitzpatrick
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G11B20/1803 , G11B20/10222 , G11B2020/10722 , G11B2020/10759 , G11B2020/1287 , G11B2020/1289 , G11B2020/185 , H03M13/1105 , H03M13/27 , H03M13/2732 , H03M13/3905 , H03M13/4146 , H03M13/458 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output. A second detection circuit applies a phase dependent data detection algorithm to the phase shifted output such that a second output of the second data detection circuit varies from the first output at least in part due to a different phase of the data set presented to the second data detection circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种数据处理电路，其包括第一数据检测电路，该第一数据检测电路将相关数据检测算法应用于数据组，使得第一数据检测电路的第一输出根据所呈现的数据集的相位而变化第一数据检测电路。将数据集的第一阶段呈现给第一数据检测电路。这些电路还包括对第一输出应用解码算法以产生解码输出的解码器电路，以及相位移动电路，使得解码输出相移，使得提供数据组的第二相作为相移输出。第二检测电路将相位相关数据检测算法应用于相移输出，使得第二数据检测电路的第二输出至少部分地由于呈现给第二数据的数据集的相位而从第一输出变化检测电路。

84. 发明授权

US08850276B2 Systems and methods for efficient data shuffling in a data processing system 有权
标题翻译：数据处理系统中高效数据刷新的系统和方法
公开(公告)号：US08850276B2
公开(公告)日：2014-09-30
申请号：US13239683
申请日：2011-09-22
申请人： Changyou Xu , Zongwang Li , Sancar K. Olcay , Yang Han , Kaichi Zhang
发明人： Changyou Xu , Zongwang Li , Sancar K. Olcay , Yang Han , Kaichi Zhang
IPC分类号： G06F11/00 , G11C29/00 , H03M13/27 , H03M13/00 , H04L1/00 , H03M13/41 , H03M13/11 , H03M13/39
CPC分类号： H04L1/0052 , H03M13/1102 , H03M13/271 , H03M13/3905 , H03M13/41 , H03M13/6561 , H04L1/0071
摘要： Various embodiments of the present invention provide systems and methods for data processing. Such data processing includes data shuffling.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。这样的数据处理包括数据混洗。

85. 发明申请

US20130080844A1 Systems and Methods for Efficient Data Shuffling in a Data Processing System 有权
标题翻译：数据处理系统中有效数据刷新的系统和方法
公开(公告)号：US20130080844A1
公开(公告)日：2013-03-28
申请号：US13239683
申请日：2011-09-22
申请人： Changyou Xu , Zongwang Li , Sancar K. Olcay , Yang Han , Kaichi Zhang
发明人： Changyou Xu , Zongwang Li , Sancar K. Olcay , Yang Han , Kaichi Zhang
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： H04L1/0052 , H03M13/1102 , H03M13/271 , H03M13/3905 , H03M13/41 , H03M13/6561 , H04L1/0071
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes: receiving a data input having at least a first local chunk and a second local chunk, the data input also being defined as having at least a first global chunk and a second global chunk; rearranging an order of the first local chunk and the second local chunk to yield a locally interleaved data set; storing the locally interleaved data set to a first memory, such that the first global chunk is stored to a first memory space, and the second global chunk is stored to a second memory space; accessing the locally interleaved data set from the first memory; and storing the locally interleaved data set to a second memory. The first global chunk is stored to a third memory space defined at least in part based on the first memory space, and the second global chunk is stored to a fourth memory space defined at least in part based on the second memory space.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种用于数据处理的方法，包括：接收具有至少第一本地块和第二本地块的数据输入，所述数据输入还被定义为具有至少第一全局块和第二全局块; 重新排列第一本地块和第二本地块的顺序以产生本地交织的数据集; 将本地交织的数据集存储到第一存储器，使得第一全局块被存储到第一存储器空间，并且第二全局块被存储到第二存储器空间; 从所述第一存储器访问本地交错数据集; 以及将本地交织的数据集存储到第二存储器。第一全局块被存储到基于第一存储器空间至少部分地定义的第三存储器空间，并且第二全局块被存储到基于第二存储器空间至少部分地定义的第四存储器空间。

86. 发明申请

US20130232390A1 Systems and Methods for Multi-Matrix Data Processing 有权
标题翻译：多矩阵数据处理系统与方法
公开(公告)号：US20130232390A1
公开(公告)日：2013-09-05
申请号：US13412520
申请日：2012-03-05
申请人： Fan Zhang , Zongwang Li , Yang Han , Shaohua
发明人： Fan Zhang , Zongwang Li , Yang Han , Shaohua
IPC分类号： H03M13/05 , G06F11/10 , H03M13/29
CPC分类号： H03M13/09 , G06F11/1076 , G11B20/1833 , G11B20/1866 , G11B2020/185 , G11B2220/2516 , H03M13/1111 , H03M13/27 , H03M13/3707 , H03M13/3746 , H03M13/616 , H03M13/6331 , H03M13/6343 , H03M13/6561
摘要： The present inventions are related to systems and methods for data processing. As one example, a data processing system is discussed that includes a data decoder circuit and a matrix select control circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input using a selected parity check matrix to yield a decoder output. The matrix select control circuit operable to select one of a first parity check matrix and a second parity check matrix as the selected parity check matrix.
摘要翻译：本发明涉及用于数据处理的系统和方法。作为一个示例，讨论了包括数据解码器电路和矩阵选择控制电路的数据处理系统。数据解码器电路可操作以使用所选择的奇偶校验矩阵将数据解码算法应用于解码器输入以产生解码器输出。矩阵选择控制电路可操作以选择第一奇偶校验矩阵和第二奇偶校验矩阵中的一个作为所选奇偶校验矩阵。

87. 发明授权

US08854754B2 Systems and methods for local iteration adjustment 有权
标题翻译：用于局部迭代调整的系统和方法
公开(公告)号：US08854754B2
公开(公告)日：2014-10-07
申请号：US13213751
申请日：2011-08-19
申请人： Fan Zhang , Zongwang Li , Wu Chang
发明人： Fan Zhang , Zongwang Li , Wu Chang
IPC分类号： G11B5/09 , G11B20/10 , G06F9/30
CPC分类号： G06F9/30 , H03M13/1111 , H03M13/1128 , H03M13/1515 , H03M13/2957 , H03M13/41 , H03M13/6331 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data decoder circuit and a local iteration adjustment circuit. The data decoder circuit is operable to perform a number of local iterations on a decoder input to yield a data output. The local iteration adjustment circuit is operable to generate a limit on the number of local iterations performed by the data decoder circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了一种数据处理电路，其包括：数据解码器电路和局部迭代调整电路。数据解码器电路可操作以在解码器输入上执行多次局部迭代以产生数据输出。本地迭代调整电路可操作以产生由数据解码器电路执行的局部迭代次数的限制。

88. 发明授权

US08756478B2 Multi-level LDPC layer decoder 有权
标题翻译：多级LDPC层解码器
公开(公告)号：US08756478B2
公开(公告)日：2014-06-17
申请号：US13300078
申请日：2011-11-18
申请人： Chung-Li Wang , Zongwang Li , Lei Chen , Johnson Yen
发明人： Chung-Li Wang , Zongwang Li , Lei Chen , Johnson Yen
IPC分类号： H03M13/00
CPC分类号： H03M13/1117 , G06F11/1076 , H03M13/1122 , H03M13/1125 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1171 , H03M13/6577 , H03M13/658 , H03M13/6591
摘要： Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding. For example, in one embodiment an apparatus includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The check node processor includes a min finder circuit operable to identify a minimum, a next minimum and an index of minimum value in the variable node to check node messages. The variable node processor and check node processor are operable to perform layered multi-level decoding.
摘要翻译：本发明的各种实施例涉及用于解码数据的方法和装置，更具体地涉及用于多级分层LDPC解码的方法和装置。例如，在一个实施例中，装置包括可变节点处理器和校验节点处理器。可变节点处理器可操作以生成变量节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知值。校验节点处理器可用于将校验节点生成到可变节点消息，并且基于变量节点来计算校验和以检查节点消息。校验节点处理器包括可用于识别可变节点中的最小值，下一个最小值和最小值的索引以检查节点消息的最小取景器电路。可变节点处理器和校验节点处理器可操作以执行分层多级解码。

89. 发明授权

US08751913B2 Systems and methods for reduced power multi-layer data decoding 有权
标题翻译：降低功率多层数据解码的系统和方法
公开(公告)号：US08751913B2
公开(公告)日：2014-06-10
申请号：US13295160
申请日：2011-11-14
申请人： Zongwang Li , Lei Chen , Chung-Li Wang
发明人： Zongwang Li , Lei Chen , Chung-Li Wang
IPC分类号： H03M13/00
CPC分类号： H03M13/1122 , H03M13/112 , H03M13/116 , H03M13/658
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a data encoder circuit. The data encoder circuit is operable to apply an encoding algorithm to an input data set in accordance with a multi-layer code structure including a first row and a last row to yield an encoded data set. The last row of the multi-layer code structure represented in the encoded data set conforms to an identity matrix.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括数据编码器电路的数据处理系统。数据编码器电路可操作以根据包括第一行和最后一行的多层代码结构将编码算法应用于输入数据集，以产生编码数据集。在编码数据集中表示的多层代码结构的最后一行符合一个单位矩阵。

90. 发明申请

US20130061107A1 Multi-Level LDPC Layer Decoder 有权
标题翻译：多级LDPC层解码器
公开(公告)号：US20130061107A1
公开(公告)日：2013-03-07
申请号：US13300078
申请日：2011-11-18
申请人： Chung-Li Wang , Zongwang Li , Lei Chen , Johnson Yen
发明人： Chung-Li Wang , Zongwang Li , Lei Chen , Johnson Yen
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1117 , G06F11/1076 , H03M13/1122 , H03M13/1125 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1171 , H03M13/6577 , H03M13/658 , H03M13/6591
摘要： Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding. For example, in one embodiment an apparatus includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The check node processor includes a min finder circuit operable to identify a minimum, a next minimum and an index of minimum value in the variable node to check node messages. The variable node processor and check node processor are operable to perform layered multi-level decoding.
摘要翻译：本发明的各种实施例涉及用于解码数据的方法和装置，更具体地涉及用于多级分层LDPC解码的方法和装置。例如，在一个实施例中，装置包括可变节点处理器和校验节点处理器。可变节点处理器可操作以生成变量节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知值。校验节点处理器可用于将校验节点生成到可变节点消息，并且基于变量节点来计算校验和以检查节点消息。校验节点处理器包括可用于识别可变节点中的最小值，下一个最小值和最小值的索引以检查节点消息的最小取景器电路。可变节点处理器和校验节点处理器可操作以执行分层多级解码。

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