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81. 发明授权

US08463837B2 Method and apparatus for efficient bi-linear interpolation and motion compensation 有权
标题翻译：用于高效双线性插值和运动补偿的方法和装置
公开(公告)号：US08463837B2
公开(公告)日：2013-06-11
申请号：US10687953
申请日：2003-10-17
申请人： Yen-Kuang Chen , Minerva M. Yeung
发明人： Yen-Kuang Chen , Minerva M. Yeung
IPC分类号： G06F17/10
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for performing bi-linear interpolation and motion compensation including multiply-add operations and byte shuffle operations on packed data in a processor. In one embodiment, two or more lines of 2n+1 content byte elements may be shuffled to generate a first and second packed data respectively including at least a first and a second 4n byte elements including 2n−1 duplicated elements. A third packed data including sums of products is generated from the first packed data and packed byte coefficients by a multiply-add instruction. A fourth packed data including sums of products is generated from the second packed data and elements and packed byte coefficients by another multiply-add instruction. Corresponding sums of products of the third and fourth packed data are then summed, and may be rounded and averaged.
摘要翻译：一种用于执行双线性插值和运动补偿的方法和装置，包括对处理器中的打包数据的乘法运算和字节洗牌操作。在一个实施例中，2n + 1个内容字节元素的两行或更多行可以进行混洗以产生分别包括至少包括2n-1个重复元素的第一和第二4n个字节元素的第一和第二打包数据。通过乘法加法指令从第一打包数据和打包字节系数生成包括产品总和的第三打包数据。通过另一个乘法加法指令，从第二打包数据和元素和打包字节系数生成包括产品总和的第四打包数据。然后将第三和第四打包数据的相应的乘积相加，并且可以舍入和平均。

82. 发明授权

US08417891B2 Shared cache memories for multi-core processors 有权
标题翻译：用于多核处理器的共享高速缓存
公开(公告)号：US08417891B2
公开(公告)日：2013-04-09
申请号：US12335381
申请日：2008-12-15
申请人： Wenlong Li , Yu Chen , Changkyu Kim , Christopher J. Hughes , Yen-Kuang Chen
发明人： Wenlong Li , Yu Chen , Changkyu Kim , Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0815
摘要： Embodiments of shared cache memories for multi-core processors are presented. In one embodiment, a cache memory comprises a group of sampling cache sets and a controller to determine a number of misses that occur in the group of sampling cache sets. The controller is operable to determine a victim cache line for a cache set based at least in part on the number of misses.
摘要翻译：呈现用于多核处理器的共享高速缓冲存储器的实施例。在一个实施例中，高速缓存存储器包括一组采样高速缓存组和控制器，用于确定在采样高速缓存组组中出现的多少个未命中。控制器可操作以至少部分地基于错失次数来确定用于高速缓存组的受害者高速缓存行。

83. 发明授权

US08028129B2 Dynamically re-classifying data in a shared cache 有权
标题翻译：在共享缓存中动态重新分类数据
公开(公告)号：US08028129B2
公开(公告)日：2011-09-27
申请号：US12497115
申请日：2009-07-02
申请人： Christopher J. Hughes , Yen-Kuang Chen
发明人： Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定数据状态是否指示第一类数据的方法，基于该确定将数据从第二类重新分类为第一类，并将数据移动到基于重新分类，与第一请求者单元相关联的共享缓存的第一部分。描述和要求保护其他实施例。

84. 发明申请

US20110145184A1 METHODS AND SYSTEMS TO TRAVERSE GRAPH-BASED NETWORKS 有权
标题翻译：基于图表的网络的方法和系统
公开(公告)号：US20110145184A1
公开(公告)日：2011-06-16
申请号：US12637228
申请日：2009-12-14
申请人： Kisun You , Christopher J. Hughes , Yen-Kuang Chen
发明人： Kisun You , Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06N5/04 , G06N5/02
CPC分类号： G10L15/063 , G10L15/02 , G10L15/083 , G10L15/19 , G10L15/34
摘要： Methods and systems to translate input labels of arcs of a network, corresponding to a sequence of states of the network, to a list of output grammar elements of the arcs, corresponding to a sequence of grammar elements. The network may include a plurality of speech recognition models combined with a weighted finite state machine transducer (WFST). Traversal may include active arc traversal, and may include active arc propagation. Arcs may be processed in parallel, including arcs originating from multiple source states and directed to a common destination state. Self-loops associated with states may be modeled within outgoing arcs of the states, which may reduce synchronization operations. Tasks may be ordered with respect to cache-data locality to associate tasks with processing threads based at least in part on whether another task associated with a corresponding data object was previously assigned to the thread.
摘要翻译：将对应于网络状态序列的网络的弧的输入标签转换成对应于语法元素序列的弧的输出语法元素的列表的方法和系统。网络可以包括与加权的有限状态机换能器（WFST）组合的多个语音识别模型。遍历可能包括有效的电弧遍历，并且可能包括有效的电弧传播。弧可以并行处理，包括源自多个源状态并被引导到公共目的地状态的弧。与状态相关联的自环可以在状态的输出弧内被建模，这可以减少同步操作。至少部分地基于是否将与对应的数据对象相关联的另一个任务先前分配给线程，可以针对高速缓存数据位置命令任务来将任务与处理线程相关联。

85. 发明申请

US20110138128A1 Technique for tracking shared data in a multi-core processor or multi-processor system 有权
标题翻译：用于跟踪多核处理器或多处理器系统中的共享数据的技术
公开(公告)号：US20110138128A1
公开(公告)日：2011-06-09
申请号：US12592998
申请日：2009-12-07
申请人： Yen-Kuang Chen , Christopher J. Hughes , Changkyn Kim
发明人： Yen-Kuang Chen , Christopher J. Hughes , Changkyn Kim
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A technique to track shared information in a multi-core processor or multi-processor system. In one embodiment, core identification information (“core IDs”) are used to track shared information among multiple cores in a multi-core processor or multiple processors in a multi-processor system.
摘要翻译：一种在多核处理器或多处理器系统中跟踪共享信息的技术。在一个实施例中，核心识别信息（“核心ID”）用于在多处理器系统中的多核处理器或多个处理器中的多个核之间跟踪共享信息。

86. 发明申请

US20110078340A1 VIRTUAL ROW BUFFERS FOR USE WITH RANDOM ACCESS MEMORY 有权
标题翻译：使用随机存取存储器的虚拟缓存
公开(公告)号：US20110078340A1
公开(公告)日：2011-03-31
申请号：US12567638
申请日：2009-09-25
申请人： CHANGKYU KIM , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
发明人： CHANGKYU KIM , Albert Lin , Christopher J. Hughes , Anthony-Trung D. Nguyen , Yen-Kuang Chen , Zeshan A. Chishti , Bryan K. Casper
IPC分类号： G06F12/00 , G06F3/00 , G06F13/00
CPC分类号： G11C11/4082 , G06F1/3275 , G11C11/4085 , Y02D10/13 , Y02D10/14
摘要： Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.
摘要翻译：降低存储芯片能量消耗的方法，装置和系统，同时在执行任何工作负载的同时增加其效果带宽。方法，设备和系统可以允许存储器芯片利用多个虚拟行缓冲器来响应包含在存储器阵列块中的数据的请求。方法，装置和系统可以通过改变存储器阵列块和行缓冲器之间的数据传输大小来进一步消除或减少与将不需要的数据从存储器阵列块传送到行缓冲器相关联的成本。

87. 发明授权

US07571285B2 Data classification in shared cache of multiple-core processor 有权
标题翻译：多核处理器共享缓存中的数据分类
公开(公告)号：US07571285B2
公开(公告)日：2009-08-04
申请号：US11491043
申请日：2006-07-21
申请人： Christopher J. Hughes , Yen-Kuang Chen
发明人： Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定数据状态是否指示第一类数据的方法，基于该确定将数据从第二类重新分类为第一类，并将数据移动到基于重新分类，与第一请求者单元相关联的共享缓存的第一部分。描述和要求保护其他实施例。

88. 发明授权

US07454576B2 System and method for cache coherency in a cache with different cache location lengths 失效
标题翻译：具有不同高速缓存位置长度的高速缓存中的高速缓存一致性的系统和方法
公开(公告)号：US07454576B2
公开(公告)日：2008-11-18
申请号：US11024278
申请日：2004-12-27
申请人： Yen-Kuang Chen , Christopher J. Hughes , James M. Tuck, III
发明人： Yen-Kuang Chen , Christopher J. Hughes , James M. Tuck, III
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G06F12/0817 , G06F12/0886 , Y10S707/99952
摘要： A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.
摘要翻译：公开了一种用于在一级缓存中具有不同高速缓存位置长度的缓存系统的设计和操作的系统和方法。在一个实施例中，每个级别一个高速缓存可以包括不同长度的高速缓存位置组，能够保持二级高速缓存行的部分。状态树可以从共享向量中的数据创建。当请求从一级缓存到达时，二级缓存可以检查状态树的节点，以确定与进入请求相对应的状态树的节点是否已经是活动的。该确定的结果可以用于抑制或允许并发处理请求。

89. 发明授权

US07327787B1 Method and apparatus for motion estimation 有权
标题翻译：运动估计方法和装置
公开(公告)号：US07327787B1
公开(公告)日：2008-02-05
申请号：US09717500
申请日：2000-11-20
申请人： Yen-Kuang Chen , Hong Jiang
发明人： Yen-Kuang Chen , Hong Jiang
IPC分类号： H04N7/12 , H04N11/02 , G06K9/46
CPC分类号： H04N19/57 , H04N19/53 , H04N19/533 , H04N19/56
摘要： A method and system of motion estimation for video data compression is disclosed. Individual frames of video data are divided into blocks of pixels. One frame is searched to find a block of pixels that matches intensity with the block of pixels from a second frame. In one embodiment, a motion estimator performs a rhombus shaped search of progressively smaller range for a matching block of pixels. In one embodiment, prediction motion vector is used to reduce the search efforts. In one embodiment, the actual shape of the rhombus can be adjusted to the type of motion expected.
摘要翻译：公开了一种用于视频数据压缩的运动估计方法和系统。视频数据的各个帧被划分成像素块。搜索一帧以找到与来自第二帧的像素块匹配强度的像素块。在一个实施例中，运动估计器对于匹配的像素块对逐渐变小的范围执行菱形搜索。在一个实施例中，使用预测运动矢量来减少搜索努力。在一个实施例中，可以将菱形的实际形状调整为预期的运动类型。

90. 发明申请

US20070266206A1 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems 有权
标题翻译：在多处理器系统上分散收集非结构化流数据的智能存储器架构
公开(公告)号：US20070266206A1
公开(公告)日：2007-11-15
申请号：US11432753
申请日：2006-05-10
申请人： Daehyun Kim , Christopher Hughes , Yen-Kuang Chen , Partha Kundu
发明人： Daehyun Kim , Christopher Hughes , Yen-Kuang Chen , Partha Kundu
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0806 , G06F12/08 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0862 , G06F12/0877 , G06F12/0891 , G06F12/0897 , G06F2212/6026 , G06F2212/62 , G11C7/1072 , G11C7/1075 , Y02D10/13
摘要： A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
摘要翻译：分散/收集技术优化非结构化流式存储器访问，通过仅访问精细粒度的有用数据来提供片外带宽效率，并通过支持地址计算，数据混洗和格式转换来卸载内存访问开销。

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