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81. 发明授权

US08742475B2 Field effect transistor device and fabrication 有权
标题翻译：场效应晶体管器件和制造
公开(公告)号：US08742475B2
公开(公告)日：2014-06-03
申请号：US13554294
申请日：2012-07-20
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/42368 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L29/66477
摘要： In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.
摘要翻译：在本发明的一个方面中，场效应晶体管（FET）器件包括：第一FET，其包括设置在基板上的电介质层，设置在电介质层上的第一金属层的第一部分和设置在电介质层上的第二金属层第一金属层，包括设置在电介质层上的第一金属层的第二部分的第二FET以及将第一FET与第二FET分离的边界区域。

82. 发明授权

US08643115B2 Structure and method of Tinv scaling for high κ metal gate technology 失效
标题翻译：用于高kappa金属栅极技术的Tinv缩放的结构和方法
公开(公告)号：US08643115B2
公开(公告)日：2014-02-04
申请号：US13006642
申请日：2011-01-14
申请人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
发明人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
IPC分类号： H01L27/092
CPC分类号： H01L21/28008 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.
摘要翻译：提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。等离子体氮化的nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分包括多达15个原子％N2和位于其中的pFET阈值电压调节物质。

83. 发明申请

US20130334602A1 CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS 有权
公开(公告)号：US20130334602A1
公开(公告)日：2013-12-19
申请号：US13523048
申请日：2012-06-14
申请人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
发明人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/845
摘要： Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.

84. 发明申请

US20130328135A1 PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING 审中-公开
标题翻译：防止高K金属加工过程中的完全硅化物形成
公开(公告)号：US20130328135A1
公开(公告)日：2013-12-12
申请号：US13494312
申请日：2012-06-12
申请人： Huiming Bu , Ming Cai , Kevin K. Chan , Dechao Guo , Ravikumar Ramachandran , Liyang Song , Chun-Chen Yeh
发明人： Huiming Bu , Ming Cai , Kevin K. Chan , Dechao Guo , Ravikumar Ramachandran , Liyang Song , Chun-Chen Yeh
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L29/4966 , H01L29/51 , H01L29/665 , H01L29/66628
摘要： A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.
摘要翻译：用于晶体管器件的栅极堆叠结构包括形成在衬底上的栅极电介质层; 形成在所述栅极介电层上的第一硅栅极层; 在第一硅栅极层上形成的掺杂剂富含单层; 以及形成在所述富掺杂剂单层上的第二硅栅极层，其中所述富掺杂剂层在所述第二硅栅极层的硅化期间防止所述第一硅栅极层的硅化。

85. 发明授权

US08445371B2 Self-aligned contacts 有权
公开(公告)号：US08445371B2
公开(公告)日：2013-05-21
申请号：US12755752
申请日：2010-04-07
申请人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/3205
CPC分类号： H01L21/28008 , H01L21/28052 , H01L21/28097 , H01L21/76897 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

86. 发明申请

US20130115732A1 Method to Fabricate Multicrystal Solar Cell with Light Trapping Surface Using Nanopore Copolymer 有权
标题翻译：使用纳米孔共聚物制造具有光捕获表面的多晶太阳能电池的方法
公开(公告)号：US20130115732A1
公开(公告)日：2013-05-09
申请号：US13289324
申请日：2011-11-04
申请人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang
发明人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang
IPC分类号： H01L31/18 , B32B33/00 , C23F1/04
CPC分类号： H01L31/02363 , Y02E10/50
摘要： Multi-crystalline silicon processing techniques are provided. In one aspect, a method for roughening a multi-crystalline silicon surface is provided. The method includes the following steps. The multi-crystalline silicon surface is coated with a diblock copolymer. The diblock copolymer is annealed to form nanopores therein. The multi-crystalline silicon surface is etched through the nanopores in the diblock copolymer to roughen the multi-crystalline silicon surface. The diblock copolymer is removed. A multi-crystalline silicon substrate with a roughened surface having a plurality of peaks and troughs is also provided, wherein a distance from one peak to an adjacent peak on the roughened surface is from about 20 nm to about 400 nm.
摘要翻译：提供多晶硅加工技术。一方面，提供了一种使多晶硅表面粗糙化的方法。该方法包括以下步骤。多晶硅表面涂有二嵌段共聚物。将二嵌段共聚物退火以在其中形成纳米孔。通过二嵌段共聚物中的纳米孔蚀刻多晶硅表面以粗糙化多晶硅表面。除去二嵌段共聚物。还提供了具有多个峰和谷的具有粗糙表面的多晶硅衬底，其中粗糙表面上的一个峰到相邻峰的距离为约20nm至约400nm。

87. 发明申请

US20130087859A1 Work Function Adjustment By Carbon Implant In Semiconductor Devices Including Gate Structure 有权
标题翻译：包括门结构在内的半导体器件中的碳植入工作功能调整
公开(公告)号：US20130087859A1
公开(公告)日：2013-04-11
申请号：US13253268
申请日：2011-10-05
申请人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
发明人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
IPC分类号： H01L21/266 , H01L27/092
CPC分类号： H01L27/092 , H01L21/26506 , H01L21/28088 , H01L21/28176 , H01L21/28194 , H01L21/823857 , H01L29/1054 , H01L29/517
摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.
摘要翻译：一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。还公开了形成上述装置的方法。

88. 发明申请

US20130029488A1 Single Liner Process to Achieve Dual Stress 审中-公开
标题翻译：实现双重压力的单衬套工艺
公开(公告)号：US20130029488A1
公开(公告)日：2013-01-31
申请号：US13192744
申请日：2011-07-28
申请人： Ming Cai , Dechao Guo , Chun-chen Yeh
发明人： Ming Cai , Dechao Guo , Chun-chen Yeh
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/0217 , H01L21/3105 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/7843
摘要： Methods for imparting a dual stress property in a stress liner layer of a semiconductor device. The methods include depositing a metal layer over a compressive stress liner layer, applying a masking agent to a portion of the metal layer to produce a masked and unmasked region of the metal layer, etching the unmasked region of the metal layer to remove the metal layer in the unmasked region to thereby expose a corresponding portion of the compressive stress liner layer, removing the mask to expose the metal layer from the masked region, and irradiating the compressive stress liner layer to impart a tensile stress property to the exposed portion of the compressive stress liner layer. Methods are also provided for imparting a compressive-neutral dual stress property in a stress liner layer, as well as for imparting a neutral-tensile dual stress property in a stress liner layer.
摘要翻译：在半导体器件的应力衬垫层中赋予双重应力特性的方法。所述方法包括在压缩应力衬垫层上沉积金属层，向金属层的一部分施加掩蔽剂以产生金属层的掩蔽和未掩蔽区域，蚀刻金属层的未掩蔽区域以除去金属层在未掩蔽的区域中，从而暴露出压应力衬垫层的相应部分，去除掩模以使掩模区域露出金属层，并且照射压缩应力衬层以赋予压缩应力衬垫层的暴露部分的拉伸应力特性应力衬层。还提供了用于在应力衬垫层中赋予压缩中性双应力性质以及在应力衬垫层中赋予中性拉伸双应力性质的方法。

89. 发明授权

US08338256B2 Multi-gate transistor having sidewall contacts 有权
标题翻译：具有侧壁接触的多栅极晶体管
公开(公告)号：US08338256B2
公开(公告)日：2012-12-25
申请号：US12832829
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

90. 发明申请

US20120187505A1 Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation 审中-公开
标题翻译：自对准III-V MOSFET制造，具有原位III-V外延和原位金属外延和接触形成
公开(公告)号：US20120187505A1
公开(公告)日：2012-07-26
申请号：US13013206
申请日：2011-01-25
申请人： Dechao Guo , Shu-Jen Han , Jeehwan Kim , Kuen-Ting Shiu
发明人： Dechao Guo , Shu-Jen Han , Jeehwan Kim , Kuen-Ting Shiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/8252 , H01L21/26546 , H01L21/28575 , H01L21/3245 , H01L29/0847 , H01L29/201 , H01L29/207 , H01L29/41783 , H01L29/452 , H01L29/66446 , H01L29/66477 , H01L29/66522 , H01L29/66628 , H01L29/78
摘要： A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.
摘要翻译：一种用于形成晶体管的方法，包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物与源/漏区相邻形成的区域。该方法包括在源极/漏极区域上生长凸起的源极/漏极区域，生长的升高的源极/漏极区域包括III-V半导体材料，以及在生长的升高的源极/漏极区域上生长的金属接触。形成晶体管的另一种方法包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物与源/漏区相邻形成的区域。该方法包括在源/漏区上生长金属接触。还公开了晶体管和计算机程序产品。

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