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81. 发明公开

EP2689451A1 P-/METAL FLOATING GATE NON-VOLATILE STORAGE ELEMENT 审中-公开
标题翻译： WITH P / METALLARTIGEM浮栅的非易失性存储器元件
公开(公告)号：EP2689451A1
公开(公告)日：2014-01-29
申请号：EP12716133.9
申请日：2012-03-14
申请人： SanDisk Technologies Inc.
发明人： LEE, Sanghyun , DUNGA, Mohan , HIGASHITANI, Masaaki , PHAM, Tuan , KREUPL, Franz
IPC分类号： H01L21/28 , H01L27/115 , H01L29/423 , H01L21/8247
CPC分类号： H01L21/28273 , H01L27/11524 , H01L27/11529 , H01L29/42324
摘要： Non-volatile storage elements having a P-/metal floating gate are disclosed herein. The floating gate may have a P- region near the tunnel oxide, and may have a metal region near the control gate. A P- region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P- region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

82. 发明公开

EP2929537A1 NON-VOLATILE STORAGE NAND STRING SELECT GATE VOLTAGE LOWERED DURING PROGRAMMING 有权转让
标题翻译：编程期间降低的电压选定GATES非性存储器的NAND串的
公开(公告)号：EP2929537A1
公开(公告)日：2015-10-14
申请号：EP13798526.3
申请日：2013-11-19
申请人： SanDisk Technologies Inc.
发明人： LAI, Chun-Hung , DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko
IPC分类号： G11C16/24 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/24
摘要： Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.
摘要翻译：技术盘在游离缺失可以防止编程干扰通过从无意接通防止未选择的NAND串的选择晶体管。一个NAND串的选择晶体管的Vgs可以从一个编程脉冲被降低到下一编程脉冲多次。选择晶体管可以是漏极侧选择晶体管或源极侧选择晶体管。渐进地降低未选择的NAND串的选择晶体管的Vgs随着编程可以防止选择晶体管无意中打开。因此，编程干扰防止或减少。的Vgs可以通过施加较低的电压与选择晶体管相关联的选择线被降低。的Vgs可以通过施加更高的电压来作为编程进行与未选定NAND串相关联的位线被降低。的Vgs可以通过随着编程的施加更高的电压到公共源极线被降低。

83. 发明公开

EP2837034A1 3D NON-VOLATILE STORAGE WITH ADDITIONAL WORD LINE SELECT GATES 有权转让
标题翻译：额外的3D字线选择GATES不挥发存储器
公开(公告)号：EP2837034A1
公开(公告)日：2015-02-18
申请号：EP13717697.0
申请日：2013-04-11
申请人： SanDisk Technologies Inc.
发明人： RABKIN, Peter , HIGASHITANI, Masaaki
IPC分类号： H01L29/66 , H01L29/786 , H01L27/115 , H01L21/265 , G11C16/08
CPC分类号： H01L29/66757 , G11C16/0483 , G11C16/06 , G11C16/08 , H01L21/02532 , H01L21/02595 , H01L21/04 , H01L21/26513 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L27/1222 , H01L27/1259 , H01L29/42384 , H01L29/66477 , H01L29/66742 , H01L29/6675 , H01L29/66787 , H01L29/785 , H01L29/78642 , H01L29/78696 , H01L29/7926
摘要： Disclosed herein are 3D stacked memory devices having WL select gates (229). The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area (301) of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors (231, 402, 404). 3D decoding may be provided in a 3D stacked memory device using the WL select gates.

84. 发明授权

EP2577671B1 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHRONIZED COUPLING 有权转让
标题翻译：烧写具有同步配对非易失性存储器
公开(公告)号：EP2577671B1
公开(公告)日：2014-04-02
申请号：EP11724496.2
申请日：2011-05-23
申请人： SanDisk Technologies Inc.
发明人： MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10

85. 发明授权

EP2332146B1 DATA STATE-BASED TEMPERATURE COMPENSATION DURING SENSING IN NON-VOLATILE MEMORY 有权转让
标题翻译：数据状态基于温度补偿的非易失性存储器读出期间
公开(公告)号：EP2332146B1
公开(公告)日：2014-03-05
申请号：EP09792382.5
申请日：2009-09-09
申请人： SanDisk Technologies Inc.
发明人： DUNGA, Mohan, V. , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/26 , G11C7/04
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/26

86. 发明公开

EP2839463A1 ERASE OPERATION FOR 3D NON VOLATILE MEMORY WITH CONTROLLABLE GATE-INDUCED DRAIN LEAKAGE CURRENT 有权转让
标题翻译：清除操作与可控3D GATE感应泄露的非易失性存储器
公开(公告)号：EP2839463A1
公开(公告)日：2015-02-25
申请号：EP13717699.6
申请日：2013-04-15
申请人： SanDisk Technologies Inc.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/06 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate- induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.

87. 发明公开

EP2771884A1 BACK-BIASING WORD LINE SWITCH TRANSISTORS 审中-公开
标题翻译：带后PRELOAD字线开关晶体管
公开(公告)号：EP2771884A1
公开(公告)日：2014-09-03
申请号：EP12787969.0
申请日：2012-10-23
申请人： SanDisk Technologies Inc.
发明人： TOYAMA, Fumiaki , HIGASHITANI, Masaaki
IPC分类号： G11C16/04 , G11C16/08
CPC分类号： G11C16/0483 , G11C16/08
摘要： Back biasing word line switch transistors is disclosed. One embodiment includes word line switch transistors that are in a well in a substrate. A memory array having non-volatile storage devices may be in a separate well in the substrate. The well of the word line switch transistors may be biased separately from the well of the non-volatile storage devices. While programming the non-volatile storage devices, a negative voltage may be applied to the well of the word line switch transistors. This may reduce the voltage that needs to be applied to the gate of a WL switch transistor to pass the program voltage to the selected word line. Therefore, charge pumps can be made smaller, since the maximum voltage they need to generate is smaller. A word line switch transistor may be back-biased during a read operation to pass a negative read compare voltage to a selected word line.

88. 发明公开

EP2577671A1 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHRONIZED COUPLING 有权转让
标题翻译：烧写具有同步配对非易失性存储器
公开(公告)号：EP2577671A1
公开(公告)日：2013-04-10
申请号：EP11724496.2
申请日：2011-05-23
申请人： SanDisk Technologies Inc.
发明人： MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected tol5 a group of connected non-volatile storage elements. The set of word lines includes a selected word line(WLn), unselected word lines (WLn+1/WLn- 1) that are adjacent to the selected word line and other unselected word lines (WLunse1). After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage (Vpgm) and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels (Vint1, Vint2, Vint3 ) concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.

89. 发明公开

EP2457249A1 METHOD OF FORMING NANOSTRUCTURE-BASED NAND FLASH CELLS AND THE PERIPHERY CIRCUITS THEREOF 审中-公开
标题翻译：用于生产NAND闪存单元对纳米结构BASIS和外围电路THEREFOR
公开(公告)号：EP2457249A1
公开(公告)日：2012-05-30
申请号：EP10738085.9
申请日：2010-07-21
申请人： SanDisk Technologies Inc.
发明人： PURAYATH, Vinod, Robert , KAI, James, K. , HIGASHITANI, Masaaki , ORIMOTO, Takashi , MATAMIS, George , CHIEN, Henry
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions (CSR1-CSR5) are included in non-volatile memory devices and integrated with the fabrication of select gates (SGl) and peripheral circuitry (PGl, PG2) One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

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